Array Substrate Chip Relocation for Frameless Display

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional display panels with frameless designs either suffer from lower brightness and resolution due to optical components or appear to have a frame when not in use, affecting the visual experience.

Innovation Solution

An array substrate design where a chip is positioned on the opposite side of the base substrate from the pixel units, with signal lines connecting through via holes, allowing for a frameless display without the need for a frame portion to accommodate the chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If optical components are arranged in the peripheral region to direct light into the frame region, then frameless visual effect is achieved, but brightness and resolution in the frame region are reduced and ghosting images appear

Engineering Contradiction:
Improveframeless appearanceVSAvoidbrightness in frame region
Core Design Contradiction:
ShapeVSIllumination intensity

Solution Approach 1:

The chip is moved from the traditional planar arrangement in the peripheral region to a three-dimensional configuration on the opposite side of the base substrate. This spatial relocation eliminates the need for optical components in the frame region, achieving frameless appearance without compromising brightness or resolution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The chip is extracted from the peripheral region and relocated to the opposite side of the base substrate. This removal of the chip from the traditional location eliminates the need for optical components and frame structures, achieving true frameless display while maintaining display quality.

Inventive Principle:
Principle #2Taking out (Extraction)

2Shape

If optical components are arranged in the peripheral region to direct light into the frame region, then frameless visual effect is achieved, but resolution in the frame region is reduced and ghosting images appear

Engineering Contradiction:
Improveframeless appearanceVSAvoidresolution in frame region
Core Design Contradiction:
ShapeVSManufacturing precision

Solution Approach 1:

By relocating the chip to the opposite side of the base substrate, the design eliminates the need for optical components in the frame region. This dimensional change allows the frame region to function as a normal display area with full resolution and without ghosting artifacts.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Extracting the chip from the peripheral region removes the requirement for optical components, thereby eliminating the source of resolution degradation and ghosting images in the frame region while achieving frameless appearance.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If the chip is positioned in the peripheral region, then signal connection is achieved, but a frame portion is required to accommodate the chip, affecting the frameless appearance

Engineering Contradiction:
Improvesignal connectionVSAvoidframeless appearance
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The chip is relocated from the two-dimensional peripheral region to the opposite side of the base substrate in three-dimensional space. This allows signal connection to be maintained through via holes while eliminating the need for a frame portion, achieving true frameless appearance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The chip is positioned on the opposite side of the base substrate, with signal lines extending through via holes that penetrate the substrate. This nested configuration allows the chip to be accommodated within the substrate structure itself, eliminating the need for external frame portions.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS10141386B2Array substrate, display panel and display device
Publication Date: 2018.11.27 BOE TECHNOLOGY GROUP CO LTD
  • US10141386B2 patent drawing
  • US10141386B2 patent drawing
  • US10141386B2 patent drawing

AI summary

Disclosed is an array substrate, a display panel, and a display device. The array substrate includes: a substrate (100), a plurality of pixel units (110) disposed on a side of the base substrate (100), a chip (200) configured for providing signal to the pixel units (110), signal lines (120) corresponding to each of pixel units (110), and via holes (130) penetrating the base substrate (100). By disposing the chip (200) on the side of the base substrate (100) opposed to the pixel units (110) and electrically connecting the pixel units (110) to the chip (200) through the signal lines (120) in the via holes (130), the frame portion which is used for accommodating the chip could be omitted and a real frameless design is achieved.