Array Substrate Clock Line Layering for Stable Pixel Signal Routing
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Solution Overview
Problem
Conventional display panel technologies face issues with interference and coupling between clock signal lines and data lines due to their close proximity, leading to unstable data signals, and spacing them further results in reduced effective pixel area.
Innovation Solution
The array substrate design includes clock signal lines disposed in orthographic projection areas of trunk electrodes, parallel to data lines, on a different layer, with varying distances and configurations to minimize space occupation and prevent interference, using a multi-layered structure with specific TFT sections and trunk electrodes to optimize pixel area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If clock signal lines are disposed close to data lines to narrow frames, then frame width is reduced, but interference and coupling between clock signal lines and data lines increases causing data signal instability
Solution Approach 1:
The patent applies dimensionality change by moving clock signal lines from the same plane as data lines to a different layer (vertical dimension). Specifically, clock signal lines are disposed on a different layer from pixel electrodes, allowing them to be positioned within the orthographic projection area of trunk electrodes without increasing horizontal distance from data lines, thus maintaining narrow frames while reducing interference through spatial separation in the vertical dimension.
Solution Approach 2:
The patent employs nesting by positioning clock signal lines within the orthographic projection area of trunk electrodes. The clock signal lines are nested in the vertical projection space of the trunk electrodes, allowing compact arrangement where clock signal lines occupy the same horizontal footprint as existing electrode structures, thereby preventing additional space occupation while maintaining signal integrity.
2Reliability
If clock signal lines are spaced further from data lines to reduce interference, then data signal stability is improved, but space occupation by signal lines increases compressing effective pixel area
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension through multi-layer configuration. Clock signal lines are placed on a different layer from pixel electrodes, enabling adequate spacing for signal stability without increasing horizontal distance that would reduce effective pixel area. This layered approach allows vertical separation to provide interference protection while maintaining compact horizontal layout.
Solution Approach 2:
The patent applies segmentation by dividing the display structure into multiple layers with distinct functions. The clock signal lines are segmented into a separate layer from pixel electrodes, allowing independent optimization of each layer's positioning. This segmentation enables clock signal lines to be placed in the orthographic projection area of trunk electrodes on a different layer, achieving both interference reduction and space efficiency.
3Ease of manufacture
If clock signal lines are disposed on the same layer as pixel electrodes, then manufacturing is simplified, but interference and coupling with data lines increases
Solution Approach 1:
The patent resolves this contradiction by transitioning from two-dimensional planar arrangement to three-dimensional layered configuration. Clock signal lines are disposed on a different layer from pixel electrodes, introducing vertical separation that reduces electromagnetic interference and coupling effects while maintaining manufacturing feasibility through standard multi-layer fabrication processes.
Solution Approach 2:
The patent introduces an intermediary spatial relationship by positioning clock signal lines within the orthographic projection area of trunk electrodes on a different layer. This intermediary positioning allows clock signal lines to benefit from the shielding or isolation effect of trunk electrode structures while maintaining appropriate distance from data lines, reducing interference without requiring complete separation.
Data Source
AI summary
The disclosure provides an array substrate and a display panel. The array substrate includes a plurality of data lines, a plurality of scan lines, a plurality of clock signal lines, and a plurality of pixel units formed by the data lines and the scan lines horizontally and vertically crossing each other. The data lines are disposed between two adjacent columns of the pixel units. The scan lines are disposed between two adjacent rows of the pixel units. The clock signal lines in an opening area of the pixel units are disposed in a plurality of orthographic projection areas of a plurality of trunk electrodes, are parallel to the data lines, and are disposed in a different layer from a pixel electrode.