Array Substrate Clock Signal Line Branching for RC Delay Reduction
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Solution Overview
Problem
Existing array substrates face issues with output abnormality in shift registers due to large resistance-capacitance delays at the ends of clock signal lines, leading to inefficiencies in signal transmission and control.
Innovation Solution
The array substrate design includes a clock signal line with multiple branch transmission sections connected to cascaded shift registers, reducing the number of shift registers connected to each branch and minimizing resistance-capacitance delays, thereby improving signal transmission reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single long clock signal line is used to connect all shift registers, then the structure is simple, but large resistance-capacitance delays occur at the ends of the clock signal line causing output abnormality in shift registers
Solution Approach 1:
The clock signal line is divided into multiple separate clock signal lines, each connecting to a specific group of shift registers. This segmentation reduces the length of each individual clock signal line, thereby reducing resistance-capacitance delays and preventing output abnormality in shift registers, while maintaining reasonable structural complexity.
2Reliability
If multiple clock signal lines are used to reduce resistance-capacitance delays, then signal transmission reliability improves, but the device structure becomes more complex
Solution Approach 1:
Different clock signal lines are designed with different lengths and routing paths according to the specific location and requirements of each group of shift registers. This local optimization approach ensures that each clock signal line has appropriate length to minimize delays for its target shift registers, achieving reliable signal transmission without unnecessary overall structural complexity.
Data Source
AI summary
An array substrate includes: a substrate, at least one gate driving circuit and at least one clock signal line that are located on a same side of the substrate. The gate driving circuit includes a plurality of cascaded shift registers located in different rows, the plurality of shift registers are divided into at least two groups of shift registers, each group of shift registers includes at least one shift register, located in a same column. A gate driving circuit in the at least one gate driving circuit corresponds to at least one clock signal line. The clock signal line includes a main body transmission section configured to transmit a clock signal, and at least two branch transmission sections connected to the main body transmission section. Each branch transmission section is connected to a clock signal input terminal of each shift register in a respective group of shift registers.