Array Substrate Layout to Reduce LCD Viewing-Angle Color Distortion
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Solution Overview
Problem
Existing liquid crystal display panels suffer from color distortion at large viewing angles due to parasitic capacitance, which affects the display effect.
Innovation Solution
The array substrate design includes a base substrate with signal lines and pixel units, where the first pixel unit comprises a first pixel electrode, first and second thin film transistors, and a first connection line, all of which are electrically connected to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional array substrate design is used, then manufacturing is straightforward, but parasitic capacitance causes color distortion at large viewing angles
Solution Approach 1:
The pixel electrode is divided into multiple segments (first pixel electrode segment, second pixel electrode segment, third pixel electrode segment) that are spatially separated and independently controlled by different thin film transistors. This segmentation reduces the overlap area between signal lines and pixel electrodes, thereby reducing parasitic capacitance and color distortion at large viewing angles.
Solution Approach 2:
The patent introduces a third direction (Z-direction) perpendicular to the gate line extension direction (X-direction) and data line extension direction (Y-direction). The segmented pixel electrodes are arranged in this third dimension, allowing for reduced overlap with signal lines while maintaining effective pixel area, thus reducing parasitic capacitance without compromising display resolution.
2Reliability
If signal lines are extended to cover larger areas, then connectivity is improved, but parasitic capacitance increases
Solution Approach 1:
The signal lines are segmented into different regions (gate line regions, data line regions, discharge line regions) that are spatially separated and serve different functions. This segmentation allows each signal line to be optimized for its specific purpose while minimizing unnecessary overlap with pixel electrodes, reducing parasitic capacitance while maintaining reliable electrical connections.
Solution Approach 2:
The patent introduces connection lines (first connection line, second connection line) as intermediaries between the segmented pixel electrodes and the signal lines. These connection lines provide reliable electrical connectivity while being positioned to minimize overlap with gate lines, thus reducing parasitic capacitance between signal lines and pixel electrodes.
Data Source
AI summary
Provided is an array substrate. The array substrate includes a base substrate, a gate line, a data line, a discharge line, a first pixel electrode, a first thin film transistor, a second thin film transistor and a first connection line. A control electrode of the first thin film transistor and a control electrode of the second thin film transistor are both connected to the gate line. The first electrode of the first thin film transistor is connected to the data line. Both the second electrode of the first thin film transistor and the first electrode of the second thin film transistor are connected to the first pixel electrode by the first connection line. The second electrode of the second thin film transistor is connected to the discharge line.