Array Substrate Dual-Layer Common Electrode Line RC Delay Reduction
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Solution Overview
Problem
The existing array substrates in horizontal electric field type TFT-LCDs face issues with signal delay and distortion due to high resistance in the common electrode line, leading to increased load and greenish tint caused by coupling capacitance with data lines.
Innovation Solution
Incorporating a first and second resistance wire layer connected in parallel with the common electrode line, reducing overall resistance and alleviating RC delay, while ensuring the pixel and common electrodes are insulated from each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the common electrode line is made with conventional single-layer structure, then the manufacturing process is simple, but the resistance is large causing RC signal delay and IR drop
Solution Approach 1:
The common electrode line is segmented into multiple conductive layers (first common electrode line layer and second common electrode line layer) stacked vertically. This segmentation allows each layer to contribute to current conduction, reducing the overall resistance and RC delay while maintaining manufacturing feasibility through sequential deposition processes
Solution Approach 2:
The common electrode line is constructed as a composite structure combining multiple conductive materials in different layers. The first common electrode line layer and second common electrode line layer use different material compositions, creating a composite conductive path that reduces resistance and improves signal transmission quality
2Area of stationary object
If the common electrode line overlaps the data line, then the routing is compact, but a large coupling capacitance is generated increasing load on the common electrode
Solution Approach 1:
The common electrode line is extended into the vertical dimension by creating multiple stacked layers. This dimensional transition allows the common electrode line to achieve lower resistance and reduced coupling capacitance effects by distributing the conductive path across multiple planes, thereby improving common electrode stability while maintaining compact substrate area utilization
3Device complexity
If the resistance of common electrode line is large, then the structure is simple, but RC signal delay and IR drop occur
Solution Approach 1:
The common electrode line is divided into multiple conductive segments stacked vertically, with each segment contributing to the overall conduction. This segmentation reduces the resistance of each individual path and provides multiple parallel conduction channels, thereby reducing RC delay and IR drop while maintaining reasonable structural complexity
Solution Approach 2:
Multiple conductive material layers are combined to form the common electrode line structure. Each layer may have different material properties optimized for specific functions, creating a composite structure that achieves low resistance and high signal transmission accuracy without excessive complexity
Data Source
Figure 1~2
Figure 3
AI summary
The present invention provides an array substrate and a manufacturing method thereof, and a display device, belongs to the field of display technology, and can solve the problem of RC signal delay caused by large resistance of the common electrode itself of the existing array substrate. The array substrate comprises a pixel electrode, a common electrode provided above the pixel electrode, and a common electrode line electrically connected to the common electrode, wherein the pixel electrode and the common electrode are insulated from each other, and wherein the array substrate further comprises a first resistance wire layer, and a second resistance wire layer which is provided above the first resistance wire layer and is insulated from the first resistance wire layer, the first resistance wire layer is provided on and in contact with the common electrode line; the second resistance wire layer is electrically connected to the common electrode line through a via hole penetrating through the first resistance wire layer and an insulation layer provided between the first resistance wire layer and the second resistance wire layer.