Array Substrate Common Electrode Line Design
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Solution Overview
Problem
The existing liquid crystal display technologies face challenges in achieving uniform resistance across common electrodes, leading to complex manufacturing processes and uneven liquid crystal alignment layer coating due to the large number of via holes required for electrical connections.
Innovation Solution
The array substrate design incorporates a common electrode line formed of the same material and layer as the source and drain, with direct electrical contact to the common electrode, eliminating the need for via holes and simplifying the manufacturing process by ensuring uniform resistance and reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via holes are used to connect pixel electrode and drain, then electrical connection is achieved, but manufacturing complexity increases and coating uniformity deteriorates
Solution Approach 1:
The patent removes the via hole structure from the electrical connection path between pixel electrode and drain. By directly contacting the drain electrode with the pixel electrode through the insulating layer opening, it eliminates the need for separate via hole formation processes, thereby reducing manufacturing complexity while maintaining reliable electrical connection.
Solution Approach 2:
The insulating layer opening is formed in advance during the insulating layer formation process, and the drain electrode is positioned to extend into this opening. This preliminary preparation ensures that the electrical connection path is established before subsequent pixel electrode formation, simplifying the overall manufacturing sequence and improving process integration.
2Reliability
If multiple via holes are created for electrical connections, then connectivity is improved, but coating uniformity and manufacturing precision deteriorate
Solution Approach 1:
The patent extracts the via hole formation step from the manufacturing process by designing the drain electrode to directly contact the pixel electrode through the insulating layer opening. This eliminates multiple via hole creation steps that would otherwise be required, thereby preserving coating uniformity and manufacturing precision while achieving reliable electrical connection.
Solution Approach 2:
The insulating layer opening and the electrical connection structure are merged into a single integrated design. The drain electrode extends into the insulating layer opening, combining the insulation function and electrical connection function into one structure, thereby reducing the number of separate manufacturing steps and maintaining coating uniformity.
3Reliability
If common electrode is connected through multiple via holes, then electrical connection is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent removes the via hole formation process from the common electrode connection method. By forming the common electrode to directly contact the common electrode line through the insulating layer, it eliminates the need for separate via hole creation and filling steps, thereby simplifying the manufacturing process while ensuring reliable electrical connection.
Solution Approach 2:
The insulating layer openings for common electrode connection are formed in advance during the insulating layer formation process. The common electrode is then deposited to contact the common electrode line through these pre-formed openings, eliminating the need for subsequent via hole formation steps and simplifying the overall manufacturing process.
Data Source
AI summary
An array substrate is provided that includes a plurality of sub-pixels arranged in a matrix. Each of the sub-pixels includes a substrate, a gate, a source and a drain, and a common electrode on the substrate, a passivation layer on a side of the common electrode facing away from the substrate, and a pixel electrode on a side of the passivation layer facing away from the substrate. The array substrate further includes a common electrode line, the common electrode line being formed of a same material in a same layer as the source and the drain. The common electrode is in direct electrical contact with the common electrode line. The pixel electrode and the drain are electrically connected through a via hole in the passivation layer. A display panel and a method for manufacturing an array substrate are further provided.