Array Substrate Common Electrode Removal for Crosstalk
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Solution Overview
Problem
Current 8K products made with four masks experience horizontal crosstalk due to the difficulty in canceling coupling capacitance between active layers and data signal metal lines, causing asymmetry and display issues during the display of positive and negative frames.
Innovation Solution
The array substrate design includes a common electrode layer with strategically positioned active layers and electrode traces that reduce overlapping areas with data lines, minimizing coupling capacitance asymmetry by removing part of the common electrode layer, thereby alleviating horizontal crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If four-mask technology is used to reduce production costs, then manufacturing cost decreases, but horizontal crosstalk increases due to asymmetric coupling capacitance
Solution Approach 1:
The patent extracts and removes the common electrode layer from specific overlapping regions where it intersects with data signal metal lines. By taking out the common electrode layer from these problematic areas, the asymmetric coupling capacitance is eliminated while maintaining the four-mask manufacturing process and reducing production costs without horizontal crosstalk.
Solution Approach 2:
The patent applies local quality by making the common electrode layer non-uniform - it is present in some regions and removed in others. Specifically, the common electrode layer is removed from overlapping regions with data lines while being retained in non-overlapping regions, creating local variations in electrode structure to address the crosstalk issue without compromising overall display performance.
2Object-affected harmful factors
If the common electrode layer is removed from overlapping regions, then coupling capacitance asymmetry decreases, but device structure complexity increases
Solution Approach 1:
The patent segments the common electrode layer into distinct regions: areas where the common electrode layer is present and areas where it is removed. This segmentation is achieved by dividing the display panel into overlapping regions (where common electrode layer is removed) and non-overlapping regions (where common electrode layer is retained), simplifying the overall structure while addressing capacitance asymmetry.
3Object-affected harmful factors
If the common electrode layer is partially removed, then horizontal crosstalk is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by pre-defining the regions where the common electrode layer should be removed based on the overlap between common electrode layer patterns and data signal metal line patterns. This preliminary determination of removal regions allows for systematic manufacturing guidance, reducing the actual precision demands during production while ensuring consistent elimination of asymmetric coupling capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the asymmetry of coupling capacitance and alleviates horizontal crosstalk by minimizing overlapping positions between active layers, data lines, and common electrode layers, improving display uniformity and stability.
Implementation Method 1
There is coupling capacitance between the active material, common electrode layers, and data signal metal lines
Data Source
AI summary
An array substrate and a display panel are provided. The array substrate includes a plurality of data lines and scan lines intersecting to form a plurality of subpixel units. Each of the subpixel units includes a substrate, a common electrode layer, and an active layer. The active layer includes at least a first active layer and at least a second active layer. The first active layer is located in a thin-film transistor included in the array substrate, and at least one of the second active layers is not located at a position where the common electrode layer and the data line overlap.


