Array Substrate Common Lead-Out Line Placement for Non-Quadrangle Displays
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Solution Overview
Problem
Existing liquid crystal display devices with non-quadrangle display regions face challenges in sub-capacitance configuration, leading to increased contact resistance and display variations due to deviations in common potential, particularly in Cs-on-Common type configurations where sub-capacitance lines intersect scanning and signal lines.
Innovation Solution
An array substrate design featuring a Cs-on-Common type configuration with a non-quadrangle display region, where the common lead-out line is positioned between the scanning and signal lead-out lines, avoiding intersections and using a connection line of a different layer via an insulating film to reduce contact resistance and display variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the common lead-out line is disposed in the frame region to connect sub-capacitance lines, then the sub-capacitance can be commonly connected, but the contact resistance increases and display variations occur due to intersections with scanning and signal lead-out lines
Solution Approach 1:
The common lead-out line is extracted from the intersection region of scanning and signal lead-out lines, and disposed in a separate region (either the fourth region near the end of the substrate or between the lead-out lines but not in the intersection). This separation eliminates the harmful intersections that cause increased contact resistance and potential disconnections, while maintaining the common connection function for sub-capacitance lines.
Solution Approach 2:
The patent utilizes the spatial dimension of the frame region by disposing the common lead-out line in a specific location (fourth region or between lead-out lines) that is distinct from the intersection region. This dimensional separation in the planar layout avoids the harmful interactions at intersections while maintaining electrical connectivity.
2Ease of manufacture
If the sub-capacitance line intersects both scanning lead-out line and signal lead-out line in the frame region, then the layout is simplified, but disconnection of the line or short-circuiting between the lines may occur
Solution Approach 1:
The common lead-out line is extracted from the intersection region where scanning and signal lead-out lines cross, eliminating the risk of disconnection or short-circuiting that would occur at these intersection points. The line is instead disposed in a safe region (fourth region or between lead-out lines) where no intersections occur.
Solution Approach 2:
The patent introduces an intermediary approach by using a connection line of a different layer via an insulating film to connect the sub-capacitance line and common lead-out line. This intermediary structure avoids direct intersection with scanning and signal lead-out lines, preventing disconnection and short-circuiting while maintaining connectivity.
3Reliability
If the common lead-out line is disposed to commonly connect sub-capacitance lines, then the common potential is maintained, but manufacturing complexity increases due to detailed layout requirements
Solution Approach 1:
The patent applies local quality by specifying the exact location where the common lead-out line should be disposed (either in the fourth region or between lead-out lines but not in the intersection region). This localized specification simplifies the overall layout by providing clear placement rules rather than requiring complex routing throughout the entire frame region.
Data Source
AI summary
In the array substrate where the display region has the non-quadrangle shape, a sub-capacitance line which forms a sub-capacitance is disposed at the pixel, a intersection region of the scanning lead-out line and a signal lead-out line is located at the frame region on the outside of the display region, a common lead-out line which connects the sub-capacitance line in common is disposed at the frame region side where the scanning lead-out line is disposed, the common lead-out line is not disposed in the intersection region, but disposed in a region between a region of the scanning lead-out line and a region of the signal lead-out line while intersecting any one of the scanning lead-out line and the signal lead-out line.