Array Substrate Compensation Capacitors for Display Luminance Uniformity
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Solution Overview
Problem
High resolution liquid crystal displays experience increased power consumption and gray-scale luminance differences due to variations in capacitance between adjacent rows of pixel TFTs caused by displacement of data and scan lines, leading to signal delays and jumping voltages.
Innovation Solution
An array substrate with compensation capacitors connected to each row of scan lines, featuring a first and second metal layer with an overlap region isolated by an insulation layer, where the capacitance of the compensation capacitor in one row changes in the opposite direction to the adjacent row, matching the capacitance change of the thin film transistor capacitor, allowing for adjustment of capacitance to equalize adjacent rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data lines and scan lines are displaced to increase pixel density for high resolution displays, then pixel density and resolution are improved, but capacitance variation between adjacent rows increases causing gray-scale luminance differences
Solution Approach 1:
The patent applies local quality by making the compensation capacitor structure row-specific. Each row's compensation capacitor is designed with particular overlap areas between first and second metal layers that are tailored to that row's specific capacitance requirements. This allows different rows to have different capacitance values to compensate for the systematic variations caused by line displacement, thereby maintaining uniform gray-scale luminance across all rows despite the high pixel density achieved through line displacement.
2Measurement precision
If pixel TFT size is reduced to achieve high resolution, then pixel density is improved, but signal stability deteriorates due to increased capacitance variation
Solution Approach 1:
The patent implements preliminary anti-action by pre-compensating for the capacitance variations that will occur due to line displacement. The compensation capacitors are designed with specific overlap areas between metal layers before the display operation begins, so that their capacitance values are predetermined to counteract the systematic capacitance differences between adjacent rows. This preliminary compensation prevents signal instability and gray-scale luminance differences from occurring during display operation, thereby maintaining signal stability despite reduced pixel TFT sizes.
3Manufacturing precision
If compensation capacitor overlap area is increased to adjust capacitance, then capacitance uniformity is improved, but device complexity increases due to multi-layer metal structure
Solution Approach 1:
The patent merges the compensation capacitor structure with the existing interconnect metal layers of the display device. The first and second metal layers that form the compensation capacitors are integrated into the same metal layer stack that forms the data lines and scan lines. By overlapping regions of these existing metal layers to form the compensation capacitors, the patent avoids adding separate dedicated capacitor structures, thereby achieving capacitance uniformity compensation without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces capacitance variations between adjacent rows, minimizing gray-scale luminance differences and adverse display effects such as non-uniformity and flicker, thereby improving display quality.
Implementation Method 1
the compensation capacitor including a first metal layer and a second metal layer that are overlapped with each other to form an overlap region
Data Source
AI summary
The present disclosure provides an array substrate and a display device that can suppress the adverse effects in display due to difference in gray-scale luminance of adjacent two rows caused by variation in capacitance of adjacent two rows of TFTs as the result of displacement of the data lines. Scan lines and data lines crossing each other are arranged on the array substrate. Each row of the scan lines is provided with a gate driver circuit, wherein each row of the scan lines is further provided with a compensation capacitor connected to the gate driver circuit, the compensation capacitor including a first metal layer and a second metal layer that are overlapped with each other to form an overlap region at which the first metal layer is isolated from the second metal layer by an insulation layer, wherein the compensation capacitor in an Nth row has a capacitance that changes in a direction opposite to the direction in which the capacitance of the compensation capacitor in an N+1th row changes, and the compensation capacitor in the Nth row has a capacitance that changes in the same direction as the direction in which the capacitance of a thin film transistor capacitor in the N+1th row changes, where N is a natural number greater than or equal to 1.