Array Substrate Compensation Routing for Display Hole Uniformity
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Solution Overview
Problem
Traditional electronic devices face challenges in maintaining a high screen-to-body ratio due to the need for large wiring spaces around notches or holes for front-facing components, which affects display uniformity and efficiency.
Innovation Solution
An array substrate design with specialized signal line configurations, including first and second-type signal lines and compensation signal lines, that compensate for uneven wiring densities and reduce parasitic capacitance, allowing for reduced frame area and improved display uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a notch or hole is made on the display screen for front-facing components, then the screen-to-body ratio can be improved, but large wiring space is required around the notch or hole which worsens the screen-to-body ratio
Solution Approach 1:
The patent transitions signal lines from a two-dimensional plane arrangement to a three-dimensional stacked arrangement. Multiple signal lines are positioned at different heights (Z-axis) above the substrate, allowing them to occupy different spatial layers rather than competing for the same planar space. This vertical dimensionality change enables compact wiring around the notch area while maintaining all necessary connections.
Solution Approach 2:
The patent divides signal lines into multiple segments positioned at different heights. Instead of having all signal lines in a single layer, they are segmented across multiple vertical levels, with each segment performing a specific routing function. This segmentation allows optimized path planning for each segment, reducing the total wiring space required around the notch.
2Reliability
If signal lines are densely arranged around the notch or hole, then connectivity is improved, but display uniformity deteriorates due to uneven wiring density
Solution Approach 1:
The patent applies different wiring densities at different locations by utilizing the third dimension. Areas requiring high connectivity (around the notch) use vertically stacked signal lines to achieve dense routing, while display areas use sparser arrangements to maintain uniformity. This local differentiation of wiring density is enabled by the vertical stacking capability.
Solution Approach 2:
By moving excess wiring density to the vertical dimension through stacked signal lines, the patent allows the horizontal plane to maintain more uniform wiring distribution. The compensation signal lines extend in the second direction (horizontal) to balance density variations, while the vertical stacking handles the connectivity requirements.
3Ease of manufacture
If traditional wiring layouts are used around notches, then manufacturing is simpler, but parasitic capacitance increases which worsens display stability
Solution Approach 1:
The patent reduces parasitic capacitance by separating signal lines vertically into different height levels. Signal lines that would traditionally run parallel in the same plane (creating capacitive coupling) are instead positioned at different Z-axis heights, significantly reducing their electromagnetic interaction. This vertical separation maintains manufacturing simplicity while improving electrical performance.
Data Source
AI summary
An array substrate including: pixel circuits; first signal lines including first-type signal lines and second-type signal lines, each second-type signal line includes a first segment and a second segment separated by a hole area; first connection signal lines, at least a number of the plurality of first connection signal lines is located in a display area, each first connection signal line includes a first connection segment, a second connection segment and a third connection segment connected to each other; first compensation signal lines; an orthographic projection of the first connection signal lines on a plane where the array substrate is located does not overlap with an orthographic projection of the pixel circuits on the plane, and an orthographic projection of the first compensation signal lines on the plane does not overlap with the orthographic projection of the pixel circuits on the plane.