Array Substrate Conductive Layer Segmentation for Electrostatic Repair
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Solution Overview
Problem
Existing array substrates face challenges in repairing electrostatic breakdowns at signal line-staggered regions due to easy welding between the conductive layer and signal lines, preventing complete disconnection and subsequent repair.
Innovation Solution
The array substrate design includes a conductive layer with unfilled regions or partitioning zones that do not overlap with signal line-staggered regions, allowing for laser cutting and repair by creating a gap between the conductive layer and signal lines, thereby preventing welding and enabling effective disconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conductive layer is laid on the entire array substrate to electrically connect electrode lines and signal lines, then electrical connectivity is improved, but repairability of electrostatic breakdowns at signal line-staggered regions deteriorates due to easy welding between the conductive layer and signal lines
Solution Approach 1:
The conductive layer is segmented into multiple separate conductive regions rather than being a continuous layer. Each conductive region corresponds to a specific signal line and is electrically isolated from other conductive regions, allowing independent repair of electrostatic breakdowns without affecting other areas.
Solution Approach 2:
The conductive layer is extracted or removed from the signal line-staggered regions where electrostatic breakdowns commonly occur. This creates gap regions that prevent welding between the conductive layer and signal lines, enabling effective laser cutting and repair while maintaining electrical connectivity in other areas.
2Ease of repair
If laser cutting is performed to repair electrostatic breakdown at signal line-staggered regions, then disconnection of short-circuiting sites is attempted, but welding between the conductive layer and signal lines prevents complete disconnection
Solution Approach 1:
The conductive layer is extracted or removed from the signal line-staggered regions to create gap regions. This prevents the conductive layer from welding with signal lines during laser cutting, enabling complete disconnection of short-circuiting sites for effective repair.
Solution Approach 2:
The conductive layer is pre-configured to avoid overlapping with signal lines in staggered regions, creating gap regions beforehand. This preliminary arrangement prevents welding during subsequent laser cutting operations, ensuring complete disconnection capability for repairs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for successful laser cutting and repair of electrostatic breakdowns at signal line-staggered regions, improving the repair rate and overcoming the issue of easy welding, leading to enhanced reliability and reduced manufacturing costs.
Implementation Method 1
upon laser cutting, the conductive layer 1' is easily welded with the signal lines
Data Source
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AI summary
An array substrate is disclosed herein, which includes a substrate, a plurality of signal lines, and conductive layer. The plurality of signal lines are disposed over the substrate, and have at least two signal lines insulated and staggered from one another to thereby form at least one signal line-staggered region (100) at each site of staggering. It is configured such that a first zone formed by an orthographic projection of the at least one signal line-staggered region (100) on the substrate is configured to have a gap with a second zone formed by an orthographic projection of the conductive layer (1) on the substrate excluding the first zone. The array substrate can be a thin film transistor array substrate, where the plurality of signal lines can include a common signal line (20) and a plurality of gate lines, and the common signal line (20) can be staggered with each gate line at a signal line-staggered region (100).