Array Substrate Layout for Narrow Borders and Lower Coupling Capacitance
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Solution Overview
Problem
Existing display devices face challenges in reducing border width while maintaining display quality due to increased coupling capacitance caused by using traces formed of the same conductive layer with data lines, which adversely affect signal lines in the display region.
Innovation Solution
The array substrate design includes a dual-gate structure with traces and scan lines formed of different conductive layers, reducing the number of traces in the peripheral region and minimizing coupling capacitance between traces and data lines by using distinct conductive layers, while maintaining a narrow border.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If traces are formed of the same conductive layer with data lines to bridge scan lines, then the border width can be reduced, but the coupling capacitance between adjacent signal lines increases and display quality deteriorates
Solution Approach 1:
The patent divides the conductive layer into multiple segments by using different conductive layers for traces and data lines. Specifically, traces are formed in a first conductive layer while data lines are formed in a second conductive layer, effectively segmenting the signal transmission paths to reduce electromagnetic coupling between adjacent lines while maintaining the bridging function across the display region
Solution Approach 2:
The patent transitions from a planar arrangement where traces and data lines share the same layer to a three-dimensional stacked arrangement using multiple conductive layers. This vertical separation in the Z-dimension reduces the coupling capacitance between traces and data lines while still allowing them to extend across the display region to achieve narrow borders
2Length of stationary object
If the number of signal lines in the display region is increased to meet narrow border requirements, then the border width is reduced, but the coupling capacitance increases and adversely affects display quality
Solution Approach 1:
The patent segments signal lines into different conductive layers to reduce mutual interference. By forming traces in a first conductive layer and data lines in a second conductive layer, the signal transmission paths are separated, reducing coupling capacitance and maintaining signal integrity even when multiple signal lines are present in the display region
Solution Approach 2:
The patent introduces insulating layers as intermediary structures between the first conductive layer (traces) and the second conductive layer (data lines). These insulating layers act as mediators that electrically isolate the two conductive layers, preventing direct coupling between traces and data lines while allowing both to extend across the display region
Data Source
AI summary
An array substrate includes a substrate, a first pixel electrode, a second pixel electrode, a first scan line, a second scan line and a data line. The first and second pixel electrodes are disposed on the substrate and arranged along a first direction. The first and second scan lines are disposed on the substrate and extend along the first direction, wherein the first and second pixel electrodes are disposed between the first and second scan lines. The first and second traces are disposed on the substrate and extend along a second direction different from the first direction, wherein the first and second traces are electrically connected to the first and second scan lines, respectively, the first trace crosses and is electrically insulated from the second scan line, and the data line is disposed between the first trace and the second trace.