Array Substrate Layout for OLED Node-to-Data Line Crosstalk
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Solution Overview
Problem
In OLED display technology, cross-talk between pixel nodes and adjacent data lines leads to reduced display quality due to parasitic capacitance, which existing solutions fail to adequately address.
Innovation Solution
The introduction of an interference preventing block with a first arm and a second arm, positioned to space apart the node connecting line from adjacent data lines, significantly reduces cross-talk by acting as a barrier between the node and data lines, thereby improving display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the node connecting line is positioned close to the data lines to reduce area occupation, then the pixel circuit area is reduced, but cross-talk between the node and adjacent data lines increases due to parasitic capacitance
Solution Approach 1:
An interference preventing block is introduced as an intermediary structure between the node connecting line and the adjacent data lines. This block acts as a mediator that reduces parasitic capacitance coupling while allowing the node connecting line to maintain its position for area efficiency. The interference preventing block specifically targets and mitigates the harmful electromagnetic coupling between adjacent conductive elements.
Solution Approach 2:
The interference preventing block extends in the vertical dimension (along the first direction perpendicular to the data lines), creating spatial separation between the node connecting line and data lines without increasing the horizontal footprint. By utilizing the vertical dimension for interference prevention, the design maintains compact pixel area while reducing cross-talk through increased vertical spacing.
2Object-affected harmful factors
If the node connecting line is spaced apart from adjacent data lines to reduce parasitic capacitance, then cross-talk is reduced, but the pixel circuit area increases
Solution Approach 1:
The interference preventing block exploits the vertical dimension to achieve electrical isolation between the node connecting line and data lines. By extending the block vertically along the first direction, the design creates effective spacing for reducing parasitic capacitance without proportionally increasing the horizontal area occupied by the pixel circuit.
Solution Approach 2:
The interference preventing block functions as a thin film or planar barrier structure that provides electrical isolation between conductive elements. This thin-film approach reduces parasitic capacitance coupling while occupying minimal space, effectively decoupling the node connecting line from adjacent data lines without significantly increasing the pixel circuit footprint.
3Object-affected harmful factors
If existing solutions are used to address cross-talk, then some level of interference reduction is achieved, but the display quality is still reduced due to inadequate cross-talk mitigation
Solution Approach 1:
The interference preventing block serves as a dedicated intermediary structure specifically designed to reduce cross-talk between the node connecting line and adjacent data lines. This mediator structure provides targeted interference mitigation that existing solutions fail to deliver, thereby improving display quality by adequately addressing the cross-talk problem.
Solution Approach 2:
The interference preventing block is positioned in advance between the node connecting line and data lines to preemptively reduce parasitic capacitance coupling. By establishing this protective barrier before signal transmission occurs, the design prevents cross-talk interference from developing, thereby ensuring high display quality without relying on post-processing or compensation techniques.
Data Source
AI summary
An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective one of the plurality of voltage supply lines, connected to a first capacitor electrode through a first via, and connected to a semiconductor material layer through a second via; and an interference preventing block in a same layer as the second capacitor electrode. The respective one of the plurality of voltage supply lines is connected to the interference preventing block through a third via. The interference preventing block includes a first arm and a second arm. Along the first direction, a portion of the node connecting line at a position connecting to the semiconductor material layer through the second via is spaced apart from a first adjacent data line by the first arm, and is spaced apart from a second adjacent data line by the second arm.