Array Substrate Electrode Layout to Prevent Crosstalk and Light Loss
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Solution Overview
Problem
Conventional array substrates have a low aperture ratio, limiting the transmittance of liquid crystal displays due to the design of vertical signal lines that restrict the area of the pixel electrode.
Innovation Solution
The array substrate design includes first and second data lines and scan lines that crisscross each other, with overlapping projections of the scan lines and stem electrodes, allowing for a more efficient use of design space and eliminating the need for shielding electrodes, thereby increasing the pixel aperture ratio and reducing light loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical signal lines are designed separately from pixel electrodes, then signal transmission is achieved, but the pixel electrode area is reduced
Solution Approach 1:
The scan line is merged with the stem electrode structure, where the scan line coincides with the stem electrode in the vertical direction. This integration eliminates the need for separate vertical signal lines while maintaining signal transmission functionality, thereby maximizing the pixel electrode area.
Solution Approach 2:
The stem electrode serves dual functions: it acts as both the pixel electrode component and the vertical scan line for signal transmission. This multi-functionality reduces the number of separate components needed, increasing the effective pixel area while ensuring reliable signal delivery to each sub-pixel.
2Device complexity
If conventional GCOF design with three narrow edges and one wide edge is used, then gate driver integration is achieved, but border width cannot be sufficiently reduced
Solution Approach 1:
The patent adopts an asymmetric border design with three narrow edges and one wide edge, optimizing the placement of the gate driver circuit. The GOA structure is integrated into the narrow border region, allowing the display area to be maximized while maintaining functional gate driver integration.
Solution Approach 2:
The gate driver circuit is positioned in the border region rather than occupying additional area within the display matrix. By utilizing the peripheral dimension (border area), the patent achieves gate driver integration without compromising the active display area or requiring symmetric border design.
3Reliability
If shield electrodes are added to prevent crosstalk, then signal interference is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent removes the need for separate shield electrodes by integrating the scan line function directly into the stem electrode structure. This extraction of the scanning function from a separate component eliminates the requirement for additional shielding layers, simplifying the manufacturing process while maintaining crosstalk prevention through proper electrical isolation design.
Data Source
AI summary
An array substrate, a manufacturing method thereof, and a display panel are provided. The array substrate includes a substrate. A plurality of sub-pixels are disposed on the substrate. Each of the sub-pixels includes a pixel electrode, and the pixel electrode includes a first stem electrode disposed along a first direction. A plurality of first data lines are disposed on the substrate. Each of the data lines is connected to a group of the sub-pixels extending along the first direction. A plurality of first scan lines extending along the first direction are disposed on the substrate.