Array Substrate Data Line Segmentation for Charge Time
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Solution Overview
Problem
Conventional liquid crystal display devices face issues with color washout, increased manufacturing costs, reduced aperture ratio, and insufficient charge time due to the need for high frame rates and resolution, particularly in Full HD and 3D applications, which are exacerbated by the conventional solutions of doubling data lines and increasing gate lines.
Innovation Solution
The proposed array substrate and pixel unit configuration includes a specific arrangement of subpixels, active devices, gate lines, and data lines, allowing each gate line to charge 1.5 rows, reducing the number of data lines to ¾ of conventional 2D1G arrangements, and employing a column inversion driving method to maintain high frame rates and aperture ratios while lowering manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the number of data lines is doubled to reduce color washout, then color washout is reduced, but manufacturing costs increase and aperture ratio decreases
Solution Approach 1:
The patent segments the pixel array into multiple scanning zones (first scanning area, second scanning area, third scanning area) with different gate line configurations. Each zone uses a tailored gate line arrangement optimized for its specific requirements, allowing the system to achieve high frame rates and adequate charge time without uniformly increasing the total number of gate lines across the entire display, thereby reducing manufacturing complexity while maintaining display quality
Solution Approach 2:
The patent implements dynamic scanning control where different gate lines are activated in different time periods within each frame cycle. The first gate line scans during a first time period, the second gate line scans during a second time period, and the third gate line scans during a third time period. This dynamic time-multiplexed approach allows the system to achieve high frame rates (120Hz or 240Hz) without requiring a proportional increase in the number of physical data lines, thus avoiding increased manufacturing costs and aperture ratio reduction
2Productivity
If the frame rate is increased to 120 Hz or 240 Hz, then display quality is improved, but charge time becomes insufficient
Solution Approach 1:
The patent divides the pixel array into multiple scanning areas (first, second, and third scanning areas) that are scanned at different time periods within each frame cycle. This segmentation allows each scanning zone to be charged for a longer duration without requiring a reduction in overall frame rate, as the charging operations are distributed across different time slots rather than competing for the same time window
Solution Approach 2:
The patent implements periodic scanning where gate lines are activated in repeating cycles. The first gate line scans during a first time period, the second gate line scans during a second time period, and the third gate line scans during a third time period, with this pattern repeating at 120Hz or 240Hz frame rates. This periodic time-multiplexed scanning ensures that each pixel region receives adequate charge time while maintaining high overall frame rates
3Manufacturing precision
If the number of gate lines and data lines is increased to achieve high resolution, then display resolution is improved, but manufacturing costs increase
Solution Approach 1:
The patent segments the display into multiple scanning areas with different gate line configurations optimized for their specific resolution requirements. Edge regions use fewer gate lines with lower resolution requirements, while central regions use more gate lines for higher resolution. This segmentation allows the system to achieve high overall display resolution without uniformly increasing the number of gate lines and data lines across the entire display, thereby controlling manufacturing costs
Solution Approach 2:
The patent employs dynamic scanning control where different gate lines are activated at different time periods. The first gate line scans during a first time period, the second gate line scans during a second time period, and the third gate line scans during a third time period. This dynamic time-multiplexed approach allows the system to achieve high effective resolution through temporal separation of scanning operations without requiring a proportional increase in the number of physical gate lines and data lines, thus reducing manufacturing complexity and costs
Data Source
AI summary
An array substrate and a pixel unit of a display panel include a plurality of subpixels arranged in a pixel array (N row*M column). Only one data line is disposed in a portion of two adjacent columns of subpixels in the pixel array, and two data lines are disposed in another portion of two adjacent columns of subpixels in the pixel array.