Array Substrate Data Link Structure for LCD Non-Active Area Reduction
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Solution Overview
Problem
Existing liquid crystal display devices face limitations in reducing the non-active area while maintaining image quality, as reducing the size of data pads and link lines leads to signal delay and increased resistance, causing flicker characteristics degradation.
Innovation Solution
Implementing a two-type metal data link structure where data link lines and pads are formed on different layers, with specific metal arrangements in the active and non-active areas to reduce the non-active area without degrading image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If data pads and link lines are reduced in size to minimize non-active area, then the non-active area is reduced, but signal delay increases and resistance increases causing flicker characteristics degradation
Solution Approach 1:
The patent applies multi-layer structure to arrange data link lines and pads at different layer levels. Specifically, odd-numbered data link lines are arranged on a first layer while even-numbered data link lines are arranged on a second layer, with corresponding odd and even data pads positioned at different layer levels. This three-dimensional spatial arrangement reduces the planar area required for the non-active region while maintaining adequate signal path dimensions to prevent excessive resistance and signal delay, thereby preserving flicker characteristics.
Solution Approach 2:
The patent employs different metal materials for data link lines at different layer levels. The first data link lines on the first layer use a first metal material, while the second data link lines on the second layer use a second metal material. This composite material approach allows optimization of electrical properties such as conductivity and resistance for each layer, enabling reduced non-active area while maintaining signal integrity and preventing flicker degradation.
2Ease of manufacture
If data link lines are arranged in the same pattern at the same layer level, then manufacturing is simplified, but the non-active area cannot be reduced further
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional multi-layer arrangement. Data link lines are distributed across multiple layer levels with odd-numbered lines on the first layer and even-numbered lines on the second layer. This dimensional change enables significant reduction of the non-active area in the planar view while the manufacturing process remains relatively straightforward through standard multi-layer fabrication techniques.
Solution Approach 2:
The patent segments the data link lines into odd-numbered and even-numbered groups, assigning each group to different layer levels. This segmentation allows independent optimization of each layer's layout and reduces the required width of the non-active area, as the link lines no longer need to be accommodated in a single crowded layer but are distributed across multiple layers.
3Area of stationary object
If the width of data link lines is reduced to minimize non-active area, then the non-active area is reduced, but line resistance increases causing signal delay
Solution Approach 1:
By arranging data link lines on multiple layer levels rather than compressing them into a single layer, the patent maintains adequate line width for each individual link line while reducing the overall planar footprint of the non-active area. The vertical separation in the z-dimension (different layers) allows sufficient horizontal space on each layer for maintaining low-resistance pathways.
Solution Approach 2:
The use of different metal materials for data link lines on different layers allows optimization of electrical properties. The first metal material for odd-numbered lines and the second metal material for even-numbered lines can be selected to provide low resistance and low signal delay, compensating for any reduction in line width that occurs when distributing lines across multiple layers.
Data Source
AI summary
An array substrate for a liquid crystal display device can include a plurality of gate lines arranged in one direction to correspond to an active area on a substrate; a plurality of data lines configured to cross the plurality of gate lines in a perpendicular direction; a plurality of pixel electrodes respectively positioned at intersections between the plurality of gate lines and the plurality of data lines; and a plurality of data link lines respectively connected to a (4n−2)th data line in the active area and a (4n−2)th data pad in the non-active area, and a (4n−1)th data line in the active area and a (4n−1)th data pad in the non-active area, where n is a natural number, in which at least some of the plurality of data link lines are located at a different layer level than the plurality of data lines.