Array Substrate Data Selector Circuit Leakage Reduction
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Solution Overview
Problem
Current display technologies face challenges in achieving high resolution and efficient data signal transmission due to limitations in the design of array substrates and data selector circuits.
Innovation Solution
The proposed array substrate incorporates a data selector circuit with selection driving transistors arranged in a specific configuration, featuring strip-shaped source and drain electrodes, optimized via hole positions, and a zigzag wiring pattern to enhance data signal transmission and reduce off-state leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data selector circuit uses conventional transistor design with standard via hole positioning, then the manufacturing process is simple, but the off-state leakage current is high and resolution is limited
Solution Approach 1:
The patent positions via holes at specific locations away from the channel region rather than uniformly distributing them. The source via holes are positioned on one side of the source electrode and drain via holes on the other side, creating asymmetric local structures that reduce leakage current paths while maintaining manufacturing feasibility
Solution Approach 2:
The via hole arrangement exhibits asymmetric positioning relative to the channel region, with source and drain via holes placed at different locations optimized for their respective functions. This asymmetric design breaks symmetric leakage paths and reduces off-state current while adding geometric complexity
2Manufacturing precision
If the array substrate uses higher pixel density arrangement, then the resolution is improved, but the wiring complexity and signal transmission reliability deteriorate
Solution Approach 1:
The patent extends wiring paths in zigzag patterns across multiple directions rather than simple linear connections. This multi-dimensional routing approach allows signals to bypass adjacent transistor structures, reducing crosstalk and interference while accommodating higher pixel densities through optimized spatial utilization
Solution Approach 2:
The wiring follows curved zigzag trajectories instead of straight lines, allowing smoother transitions around transistor structures and enabling compact routing in high-density arrangements. The curved paths reduce sharp corners and stress concentrations while maintaining signal integrity
3Area of moving object
If the via holes are positioned closer to the channel region, then the transistor area is reduced, but the current loss increases
Solution Approach 1:
The patent optimizes the distance parameter between via holes and channel region to achieve the best balance. By positioning via holes at specific distances away from the channel rather than immediately adjacent, the design reduces resistive losses and leakage currents while minimizing the area penalty through compact overall transistor layout
Data Source
AI summary
An array substrate and a display. A peripheral region of the array substrate includes a data selector circuit. The data selector circuit includes a plurality of selection driving transistors arranged in a row direction and a column direction, and each selection driving transistor includes a semiconductor layer, a source electrode and a drain electrode. The source electrode is connected to the semiconductor layer through source via holes, and the drain electrode is connected to the semiconductor layer through drain via holes. A minimum distance between the channel region and an edge of the source via hole furthest from the channel region is greater than a minimum distance between the channel region and an outer edge of the source electrode. An acute included angle is formed between the row direction and a line connecting centers of the source via hole and the drain via hole.