Array Substrate Fabrication via Dual-Temperature Annealing for GOA Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Oxide semiconductor TFTs in the gate driver on array (GOA) area of display devices are prone to forward bias drifting, leading to potential failure due to significant forward bias, which existing technologies have not adequately addressed.
Innovation Solution
A method for fabricating an array substrate involving the formation of a first oxide semiconductor active layer, followed by a first annealing process at a high temperature, then a second annealing process at a lower temperature, with specific annealing durations and techniques using infrared light or excimer laser, to reduce forward bias drifting and improve stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single annealing process is performed on the oxide semiconductor active layer, then the manufacturing process is simple, but the forward bias stability is insufficient
Solution Approach 1:
The annealing process is divided into two distinct stages: a first annealing process at a first temperature, and a second annealing process at a second temperature (lower than the first). This segmentation allows each annealing step to address specific aspects of forward bias stability, with the higher temperature first annealing providing initial stabilization and the lower temperature second annealing providing additional refinement, thereby resolving the contradiction between process simplicity and reliability improvement
Solution Approach 2:
The invention changes the temperature parameter between the two annealing processes, with the second annealing performed at a lower temperature than the first. This parameter change enables different thermal effects to be applied at different stages, optimizing the overall annealing effect for forward bias stability without requiring excessively complex process equipment or conditions
2Reliability
If high temperature annealing is performed to improve stability, then the forward bias stability improves, but the risk of substrate damage or material degradation increases
Solution Approach 1:
By segmenting the annealing process into two stages with different temperatures, the invention applies a moderate first annealing at a lower temperature to provide initial stabilization without excessive thermal stress, followed by a second annealing at an even lower temperature for refinement. This segmentation prevents the substrate damage risk associated with prolonged or repeated high-temperature exposure while still achieving the desired forward bias stability improvement
Solution Approach 2:
The invention changes the temperature parameter downward for the second annealing process compared to the first annealing process. This parameter change ensures that the most critical stabilization occurs at moderate temperatures, while the subsequent lower-temperature annealing provides additional stability improvement without introducing significant thermal damage risk to the substrate or other materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the forward bias stability of the TFTs in the GOA area, thereby increasing the device's lifetime and reliability by reducing forward bias drifting.
Implementation Method 1
performing a first annealing process on the first oxide semiconductor active layer at a first temperature
Implementation Method 2
performing a second annealing process on the first oxide semiconductor active layer at a second temperature, wherein the second temperature is lower than the first temperature
Data Source
AI summary
A method for fabricating an array substrate is disclosed. The method comprises: forming a first oxide semiconductor active layer of a first TFT in a GOA area of a substrate; performing a first annealing process on the first oxide semiconductor active layer at a first temperature; forming a first insulating layer which covers the first oxide semiconductor active layer; performing a second annealing process on the first oxide semiconductor active layer at a second temperature, wherein the second temperature is lower than the first temperature. This improves a forward bias stability of the first TFT and increases the device lifetime.