Array Substrate with Dual Dielectric Layers for In-Cell Touch

The patent applies local quality by using different dielectric materials with different dielectric constants in different regions. Specifically, a first insulator layer with low dielectric constant is positioned between the signal transmission line and common electrode to reduce parasitic capacitance, while a second insulator layer with high dielectric constant is positioned between the common electrode and pixel electrode to maintain storage capacitance. This spatial differentiation of material properties resolves the contradiction between integration and parasitic capacitance reduction.

The patent employs composite materials by combining insulator layers with different dielectric constants in a multilayer structure. The composite insulation system consists of a low-k material (such as silicon oxide or fluorinated silicon oxide) for parasitic capacitance reduction and a high-k material (such as silicon nitride or hafnium oxide) for storage capacitance maintenance, effectively resolving the contradiction between integration benefits and parasitic capacitance issues.

The patent maintains touch sensitivity while using standard manufacturing processes by applying local quality through selective dielectric material placement. The low-k material in the first insulator layer is deposited only in regions where signal transmission lines contact common electrodes, minimizing parasitic capacitance locally without requiring complete process redesign, thus preserving both ease of manufacture and touch sensitivity.

The patent improves touch sensitivity by changing the dielectric constant parameter of the insulator material in the first insulator layer. By selecting materials with lower dielectric constants (such as silicon oxide with k≈3.9 or fluorinated silicon oxide with k<3.5) compared to conventional materials, the parasitic capacitance is reduced, thereby enhancing touch sensitivity while remaining compatible with existing manufacturing capabilities.