Array Substrate With Dual Gate Insulators For Etching Protection
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Solution Overview
Problem
The existing array substrate fabrication processes face challenges in forming vias for connecting source-drain electrodes to active layers, which can damage the metal oxide active layer during etching and lead to transistor malfunctions due to the complexity of the etching process and the need for deep vias.
Innovation Solution
The array substrate design incorporates a second gate insulating layer made of SiOx, which is thicker and protects the metal oxide active layer during etching, allowing for shallower vias and simplifying the etching process, while also forming source and drain electrodes in a single patterning process with the gate electrode, reducing the complexity of the fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used to form vias for connecting source-drain electrodes to active layers, then the connection can be established, but the metal oxide active layer is damaged during etching and transistor malfunctions occur
Solution Approach 1:
A gate insulating layer is introduced as an intermediary protective layer between the etching process and the metal oxide active layer. This gate insulating layer serves as a barrier that prevents direct contact between the etching solution and the sensitive metal oxide active layer, thereby protecting the active layer from damage while still allowing via formation through controlled etching of the gate insulating layer itself.
Solution Approach 2:
The gate insulating layer is formed beforehand as a protective cushion layer before the etching process. This pre-formed protective layer absorbs the harmful effects of the etching process, preventing direct damage to the metal oxide active layer. The gate insulating layer is designed with sufficient thickness to withstand the etching process while being removable or penetrable to allow subsequent electrical connections.
2Reliability
If deep vias are formed to connect source-drain electrodes to active layers, then electrical connection can be established, but the etching process complexity increases
Solution Approach 1:
The solution shifts the etching dimension by forming vias through the gate insulating layer rather than through deep paths to directly reach the active layer. The gate insulating layer acts as an intermediate etching target at a shallower depth, simplifying the etching process while maintaining electrical connection reliability through subsequent conductive layer formation that bridges the source-drain electrodes to the active layer via the protected interface.
Data Source
AI summary
An array substrate includes a base substrate; a first thin film transistor on the base substrate and including a first active layer, a first gate electrode, a first source electrode and a first drain electrode; a second thin film transistor on the base substrate and including a second active layer, a second gate electrode, a second source electrode and a second drain electrode; a first gate insulating layer between the first active layer and the first gate electrode; and a second gate insulating layer between the second active layer and the second gate electrode, the second gate insulating layer being different from the first gate insulating layer. The first source electrode, the first drain electrode, and the second gate electrode are in a same layer. The first source electrode and the first drain electrode are on a side of the second gate insulating layer distal to the base substrate.