Array Substrate Layout for Uniform Dual-Gate Display Driving
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Solution Overview
Problem
Existing display panels using dual-gate line driving methods suffer from alignment deviations in thin film transistor layouts, leading to parasitic capacitance differences and poor display performance issues such as vertical lines, flickering, and afterimages.
Innovation Solution
An array substrate design with a dual-gate line driving method that incorporates a 'square wavy-shaped' data line arrangement, where each pixel group has two sub-pixels connected to a single data line, and gate lines are arranged in an odd-even alternating manner to reduce parasitic capacitance and improve display uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a dual-gate line driving method is used to reduce the number of data lines, then the number of driving chips and cost are reduced, but alignment deviations in thin film transistor layouts cause parasitic capacitance differences leading to poor display performance
Solution Approach 1:
The patent applies local quality by making the first and second transistors in each pixel group have opposite orientations (first transistor oriented in a first direction, second transistor oriented in a second direction opposite to the first direction). This local differentiation compensates for alignment deviations and reduces parasitic capacitance differences, thereby improving display performance uniformity while maintaining the dual-gate line driving method's simplicity
Solution Approach 2:
The patent introduces asymmetry in the orientation of transistors within pixel groups. By orienting the first transistor in one direction and the second transistor in the opposite direction, the design creates an asymmetric structure that balances out parasitic capacitance effects caused by alignment deviations, resolving the contradiction between simplified driving and performance uniformity
2Quantity of substance
If transistors are arranged to connect sub-pixels to data lines in a dual-gate line driving method, then the number of data lines is halved, but parasitic capacitance differences cause vertical lines, flickering, and afterimages
Solution Approach 1:
The patent changes the orientation parameter of transistors to reduce parasitic capacitance differences. By setting the first transistor to extend in a first direction and the second transistor to extend in an opposite second direction, the parasitic capacitance effects are balanced, eliminating display defects while maintaining reduced data line quantity
Solution Approach 2:
The patent converts the potentially harmful effect of alignment deviations into a beneficial outcome by strategically orienting transistors in opposite directions. This orientation strategy transforms the parasitic capacitance differences that would cause display defects into a balanced configuration that improves display uniformity
Data Source
AI summary
An array substrate includes sub-pixels, gate lines and data lines. The sub-pixels form pixel groups each including the first and second sub-pixels. The first sub-pixel includes a first transistor and a first electrode group including a first pixel electrode and a first common electrode. The second sub-pixel includes a second transistor and a second electrode group including a second pixel electrode and a second common electrode. The gate lines form gate line groups each including a first gate line and a second gate line. At least part of the data lines each include: first data segments between a i-th column of sub-pixels and a (i+1)-th column of sub-pixels, second data segments between a (i−j)-th column of sub-pixels and a (i−j−1)-th column of sub-pixels, and third segments. An overlapping area of the first pixel electrode and first common electrode equals that of the second pixel electrode and second common electrode.