Array Substrate Dual-Gate Pre-Charging for LCD Flickering

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In Thin Film Transistor Liquid Crystal Displays (TFT-LCDs), especially those with wide viewing angles, insufficient charging of pixels leads to poor display quality, including low contrast ratios and flickering, exacerbated by the Data Line Reducing technology that shortens gate line scan times.

Innovation Solution

An array substrate with a WXGA Dual-Gate configuration, where two pixels form a set with a common electrode and pixel electrode, and multiple switch transistors are strategically placed to ensure simultaneous charging and pre-charging of pixels, using a dual-gate line setup to apply constant voltage and reduce charging time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If Data Line Reducing technology is employed to increase viewing angle, then the number of data lines is reduced, but the scan speed of gate lines must be doubled or tripled which reduces pick-up time and causes insufficient pixel charging

Engineering Contradiction:
Improveviewing angleVSAvoidpixel charging sufficiency
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements pre-charging of pixels during the period when the previous gate line is being scanned. The pre-charge transistor transfers charge from the common electrode to the pixel electrode in advance, so that when the current gate line reaches the pixel, the pixel is already partially charged. This preliminary action ensures sufficient pixel charging even with reduced pick-up time from Data Line Reducing technology.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the number of gate lines is doubled or tripled to maintain resolution with Data Line Reducing, then viewing angle improves, but charging time per gate line is reduced to a half or third causing poor display quality

Engineering Contradiction:
Improvegate line scan speedVSAvoidimage display quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent ensures continuous charging action by implementing pre-charging that occurs simultaneously with the scanning of the previous gate line. The pre-charge transistor remains active during the scan period, continuously transferring charge to pixels in advance. This continuous useful action compensates for the reduced charging time per gate line, maintaining image display quality even with doubled or tripled gate line count.

Inventive Principle:
Principle #20Continuity of useful action

3Speed

If pick-up time of each gate line is reduced to maintain refresh rate with more gate lines, then scan speed increases, but pixels cannot be charged sufficiently leading to low contrast ratio and flickering

Engineering Contradiction:
Improvegate line scan speedVSAvoidcontrast ratio
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The pre-charge transistor transfers charge from the common electrode to the pixel electrode during the scan period of the previous gate line, performing the charging action in advance. This preliminary charging ensures that when the current gate line reaches the pixel with reduced pick-up time, the pixel already has sufficient charge to maintain proper contrast ratio and eliminate flickering.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9500922B2Array substrate, liquid crystal display panel and display device
Publication Date: 2016.11.22 BOE TECHNOLOGY GROUP CO LTD
  • US9500922B2 patent drawing
  • US9500922B2 patent drawing
  • US9500922B2 patent drawing

AI summary

An array substrate, a LCD panel and a display device are disclosed. The array substrate includes: a substrate, a plurality of pixels disposed on the substrate and defined by a plurality of gate lines and a plurality of data lines. A common electrode and a pixel electrode are disposed in each pixel region. Two pixels at adjacent rows in a same column form a pixel set. A first gate line and a second gate line are disposed between the two pixels of the pixel set. The data line is disposed on the same side of the two pixels. A first switch transistor and a third switch transistor are disposed in one pixel region of the pixel set and at least a second switch transistor is disposed in the other pixel region.