Array Substrate Dual Scanning Lines Black Matrix Reduction
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Solution Overview
Problem
The increasing size of TFT-LCD display panels leads to a large load on scanning lines, resulting in high parallel capacitance and a relatively low screen display rate due to the need for multiple scanning lines, which also increases the width of black matrix regions, thereby reducing the screen display rate.
Innovation Solution
The implementation of an array substrate with two scanning lines per row of pixel units, where the switch elements of first-type and second-type pixel units are connected to opposite scanning lines, and the active layer structures of adjacent rows share a common region between the scanning lines, reducing the width of the light-shielding region and increasing the light-emitting area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two scanning lines are disposed for each row of pixel units to reduce the load on scanning lines, then the load on scanning lines is reduced, but the width of black matrix regions increases, resulting in a relatively low screen display rate
Solution Approach 1:
The patent divides each row of pixel units into two separate groups, with each group controlled by a dedicated scanning line. This segmentation reduces the load on each scanning line while maintaining efficient pixel control, resolving the contradiction between reducing scanning line load and maintaining screen display rate.
Solution Approach 2:
The patent introduces a column direction division where pixel units are arranged in alternating columns and controlled by scanning lines from opposite sides. This dimensional rearrangement allows two scanning lines to serve each row while minimizing the black matrix region width through optimized spatial arrangement.
2Area of stationary object
If the size of the display panel increases, then the display area is enlarged, but the number of scanning lines and data lines greatly increases, resulting in a relatively large load on the scanning lines and a relatively large parallel capacitance
Solution Approach 1:
The patent segments the pixel units into alternating columns and assigns scanning lines to control specific segments. This segmentation strategy allows the display panel to be enlarged while distributing the scanning line load across multiple dedicated lines, preventing excessive parallel capacitance accumulation.
Solution Approach 2:
The patent implements a dynamic scanning approach where scanning lines are activated in a controlled sequence to drive pixel units in alternating columns. This dynamic control method manages the increased number of scanning lines and data lines by optimizing the scanning sequence, thereby controlling the load and parallel capacitance even as display panel size increases.
Data Source
AI summary
Disclosed is an array substrate. The array substrate includes a substrate and a pixel unit array. A first side of each row of pixel units is provided with a first scanning line corresponding to the row of pixel units, and the first scanning line is connected to switch elements of first-type pixel units in the row of pixel units; and the second side of each row of pixel units is provided with a second scanning line corresponding to the row of pixel units, and the second scanning line is connected to switch elements of second-type pixel units in the row of pixel units. An active layer structure of the switch element of a second-type pixel unit in an ith row of pixel units has a common region with an active layer structure of the switch element of a first-type pixel unit in an (i+1)th row of pixel units.