Array Substrate Layout for Narrow-Bezel Dual-Sided Driving
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Solution Overview
Problem
Existing electronic paper display panels face challenges in achieving dual-sided driving while minimizing bezel size and preventing signal interference during the manufacturing process.
Innovation Solution
The array substrate is designed with integrated driver chips and connection lines arranged in a criss-cross pattern, where some connection lines are located in the fan-out area and display area, reducing the non-display area and minimizing signal interference by equalizing the length and spacing of connection lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-sided driving structure is implemented, then the scan line damage risk is reduced, but the bezel area increases
Solution Approach 1:
The patent extends connection lines from the traditional single-side configuration into the display area through multiple layers. The third connection lines penetrate through the display area in vertical dimension, allowing driver chips to be positioned at edges while maintaining compact bezel area. This multi-layer spatial arrangement enables dual-sided driving without requiring large bezel space.
Solution Approach 2:
The connection path is segmented into multiple types: first connection lines in the non-display area, second connection lines entirely in the non-display area, and third connection lines extending into the display area. This segmentation allows different connection paths to serve different functions, enabling compact dual-sided driving configuration while maintaining reliability.
2Area of stationary object
If connection lines are extended into the display area, then the non-display area is reduced, but signal interference increases
Solution Approach 1:
The patent utilizes multi-layer structure to route third connection lines through different vertical levels. By distributing connection lines across multiple layers rather than concentrating them in a single plane, the patent reduces parasitic capacitance and signal interference while minimizing the non-display area. The multi-dimensional routing allows connection lines to coexist with display elements without excessive interference.
3Ease of manufacture
If connection lines of different lengths are used, then routing flexibility is improved, but electric field uniformity deteriorates
Solution Approach 1:
The patent applies different connection line configurations to different local regions: first connection lines for data lines in the non-display area, and third connection lines with specific length constraints for scan lines extending into the display area. By optimizing connection line lengths and positions locally for each region's specific requirements, the patent achieves both routing flexibility and electric field uniformity in their respective areas.
Data Source
AI summary
An array substrate includes a base, an integrated driver chip, multiple data lines, scan lines, first connection lines, second connection lines, and third connection lines. The third connection lines are disposed in a different layer than the scan lines. Two ends of each first connection line are connected to the integrated driver chip the corresponding data line, respectively. Two end of each second connection line are connected to the integrated driver chip and the corresponding scan line, respectively. Two ends of each third connection line are connected to the integrated driver chip and the other end of the corresponding scan line, respectively. Each scan line is connected to one respective second connection line and one respective third connection line. Each second connection line is entirely disposed in the non-display area. Each third connection line is partially disposed in the fan-out area, and partially disposed in the display area.