Array Substrate Dual TFT Pixel Architecture for Fast Data Writing
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Solution Overview
Problem
The manufacturing process for liquid crystal display (LCD) active layers is not mature enough, leading to low product yield and slow data signal writing due to the need for adjustments in material changes, which affects the conductivity of Thin Film Transistors (TFTs).
Innovation Solution
An array substrate design with two thin film transistors in each sub-pixel region, where gate electrodes of adjacent rows share a gate line, allowing simultaneous charging and pre-charging of sub-pixel regions, reducing the time required for charging and enabling faster data signal writing without affecting display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the material of the active layer is changed to improve TFT conductivity, then the writing speed of data signals is improved, but the manufacturing process becomes less mature and product yield decreases
Solution Approach 1:
The sub-pixel region is divided into two separate TFTs instead of using one TFT per pixel. This segmentation allows independent control and charging paths, enabling faster data signal writing through optimized charge distribution while maintaining stable manufacturing processes for each individual TFT structure
Solution Approach 2:
The gate electrode is designed to simultaneously charge two adjacent sub-pixel regions in advance. This preliminary action allows both sub-pixels to be pre-charged before the actual display update, reducing the overall charging time and enabling faster data signal writing without requiring material changes that would compromise manufacturing maturity
2Loss of time
If the charging time of sub-pixel regions is reduced to enable faster data writing, then the writing speed is improved, but the manufacturing complexity increases
Solution Approach 1:
The gate electrode structure is merged to serve dual functions: it controls one sub-pixel in the current row while simultaneously charging the corresponding sub-pixel in the adjacent row. This merging of functions reduces the need for additional separate charging mechanisms, achieving faster charging without proportionally increasing manufacturing complexity
Solution Approach 2:
The gate line is designed with multi-functionality to control and charge multiple sub-pixel regions across different rows. This universal gate structure performs multiple charging tasks simultaneously, reducing overall charging time while avoiding the need for dedicated complex charging circuits for each sub-pixel
Data Source
AI summary
An array substrate, a display panel and a display device are provided. The array substrate includes a plurality of gate lines and a plurality of data lines. The plurality of gate lines and the plurality of data lines define rows of sub-pixel regions, each of the sub-pixel regions includes two thin film transistors and a pixel electrode, and the two thin film transistors are both connected with the pixel electrode. Gate electrodes of two thin film transistors in an (n)th row of sub-pixel regions of the rows of sub-pixel regions are respectively connected with an (n)th gate line and an (N+1)th gate line of the plurality of gate lines, K≥n≥1, n and K are integers, and K is an amount of rows of the sub-pixel regions.