Array Substrate Dynamic Storage Capacitance for LCD Power Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The insufficient capacitance of storage capacitors in liquid crystal displays limits the reduction of refresh rate, resulting in unnecessary high power consumption, especially when displaying still images, as the capacitors cannot continuously supply power between gate driving pulse signals.
Innovation Solution
The array substrate incorporates additional switching elements and transparent electrodes to dynamically form storage capacitances between pixel electrodes and common or gate lines, allowing for adjustable total capacitance based on refresh rates, enabling power supply during low refresh rates by forming and disconnecting storage capacitances as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the refresh rate of LCD is reduced, then power consumption is reduced, but the storage capacitor cannot continuously supply power to the pixel liquid crystal due to insufficient capacitance
Solution Approach 1:
The patent combines multiple storage capacitors in parallel to form a composite storage capacitor with larger total capacitance. This composite capacitor merges the functions of individual capacitors to provide sufficient charge storage even at low refresh rates, resolving the contradiction between energy savings and reliable power supply.
Solution Approach 2:
The patent introduces switching elements that dynamically adjust the capacitance configuration based on refresh rate requirements. At low refresh rates, additional capacitors are activated to provide sufficient storage; at high refresh rates, the system uses only the basic storage capacitor, optimizing power consumption dynamically.
2Reliability
If the LCD always works under high refresh rate, then the storage capacitor can continuously supply power, but unnecessary power consumption occurs when displaying still pictures
Solution Approach 1:
The patent implements dynamic refresh rate adjustment based on image content. When displaying still pictures, the system switches to low refresh rate mode with enhanced storage capacitance activated. When displaying moving images, the system automatically increases refresh rate, dynamically optimizing the balance between power consumption and display quality.
Solution Approach 2:
The patent changes the operational parameters of the display system by adjusting refresh rate and capacitance configuration based on display requirements. This allows the system to operate efficiently at low refresh rates for still images while maintaining high refresh rate capability when needed, reducing overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows liquid crystal displays to operate efficiently at lower refresh rates, reducing power consumption by increasing total capacitance when necessary, ensuring continuous power supply to the liquid crystals between gate driving pulse signals.
Implementation Method 1
there is a storage capacitor Cs (with capacitance of about 0.5 pF) on each pixel liquid crystal of a LCD, as such, power is supplied to the pixel liquid crystal via the storage capacitor Cs after the gate driving pulse signal vanishes
Data Source
AI summary
The present invention discloses array substrate, display device and method for controlling refresh rate of an array substrate. The array substrate includes; a plurality of pixel structures each including gate line, data line, common electrode line, first switching element at intersection of the gate line and the data line, pixel electrode, second switching element, and first transparent electrode. Gate, source and drain of the first switching element are connected to the gate line, the date line and the pixel electrode, respectively. Gate, source and drain of the second switching element are connected to second switching controlling line, common electrode signal terminal and the first transparent electrode, respectively. A first storage capacitance is formed between the pixel electrode and the common electrode line and/or between the pixel electrode and the gate line, and a second storage capacitance is formed between the pixel electrode and the first transparent electrode.