Array Substrate Common Electrode Layout for Low-Resistance Annealing
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Solution Overview
Problem
Conventional display devices face issues with high resistance in common electrodes due to poor contact between Cu traces and planarization layers, leading to crystallization of ITO and etching residues, and the inability to anneal the common electrode, resulting in large resistance.
Innovation Solution
An array substrate design with a thin first common electrode layer, a metal unit, and a thicker second common electrode layer, where the metal unit is covered by the second layer to prevent oxidation during annealing, and the layers are connected in parallel to reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Cu trace is prepared directly on PFA planarization layer, then contact resistance is reduced, but Cu cannot be directly prepared on PFA due to poor contact
Solution Approach 1:
The patent introduces an ITO common electrode layer as an intermediary between the Cu trace and PFA planarization layer. The ITO layer can be directly prepared on PFA and provides a suitable surface for subsequent Cu deposition, thereby enabling reliable electrical contact while maintaining manufacturing feasibility through standard sequential deposition processes.
2Productivity
If Cu trace is prepared using PVD process, then Cu film is deposited, but ITO temperature rises causing crystallization and etching residues
Solution Approach 1:
The patent segments the common electrode structure into multiple layers: a thin first ITO common electrode layer (50-100 nm) beneath the Cu trace and a thicker second ITO common electrode layer (400-700 nm) covering the Cu trace. This segmentation allows the thin first layer to be etched away without residues after Cu deposition, while the thicker second layer remains to provide continuous electrical connection and prevent oxidation.
Solution Approach 2:
The patent applies different thicknesses of ITO in different locations: a thin first layer (50-100 nm) where etching is needed and a thicker second layer (400-700 nm) where oxidation prevention is needed. This local quality differentiation enables precise control over etching behavior and oxidation resistance in different regions of the common electrode.
3Reliability
If common electrode is annealed to reduce resistance, then conductivity is improved, but Cu trace oxidizes increasing resistance
Solution Approach 1:
The patent uses the second ITO common electrode layer as a protective intermediary that covers the Cu trace during annealing. This second layer acts as a barrier preventing oxygen from reaching and oxidizing the Cu trace, while allowing the annealing process to proceed and reduce resistance in both the ITO layers and Cu trace.
Solution Approach 2:
The patent creates a composite structure consisting of ITO and Cu layers arranged in a specific configuration. The ITO layers provide both electrical conductivity and protective functions, while the Cu trace provides low resistance. The composite structure enables simultaneous achievement of low resistance through annealing and oxidation protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces the risk of etching residues and oxidation, allowing for reduced resistance in the common electrode layers through annealing, enhancing the overall conductivity.
Implementation Method 1
since the Cu trace is directly exposed from the surface of the common electrode, and annealing the common electrode causes oxidation to Cu, annealing cannot be performed on the common electrode
Implementation Method 2
The Cu trace is usually prepared using a physical vapor deposition (PVD) process
Implementation Method 3
Cu atoms bombard the indium tin oxide (ITO), the temperature of the ITO rises, resulting in crystallization of the ITO
Implementation Method 4
annealing the common electrode causes oxidation to Cu, annealing cannot be performed on the common electrode
Implementation Method 5
annealing the common electrode layers through annealing, allowing for reduced resistance in the common electrode layers
Data Source
AI summary
The present invention relates to an array substrate and a preparation method thereof, and a display panel. The array substrate of the present invention includes a substrate, a thin film transistor layer, a planarization layer, a first common electrode layer, a metal unit, and a second common electrode layer. According to the present invention, the first common electrode layer under the metal unit is thinned. Therefore, the crystallization thickness of the first common electrode layer is reduced, and the difficulty of etching the first common electrode layer is reduced, thereby reducing the risk of remaining of the first common electrode layer.