Array Substrate Electrode Integration for OLED Aperture Ratio

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Solution Overview

Problem

The existing array substrate for OLED displays requires a separate metal connecting line to connect two thin film transistors, which complicates the manufacturing process and may lead to short-circuiting, necessitating the use of insulating materials like a black matrix to avoid short-circuiting.

Innovation Solution

The array substrate integrates the gate electrode of the second thin film transistor with the source or drain electrode of the first thin film transistor on the same layer, eliminating the need for a separate metal connecting line and simplifying the manufacturing process, while also improving the aperture ratio and effective light-emitting display regions by rearranging the power and data lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate metal connecting line is used to connect the drain electrode of the first TFT to the gate electrode of the second TFT, then the electrical connection between the two TFTs is achieved, but the device complexity increases and the manufacturing process becomes more complex

Engineering Contradiction:
Improveelectrical connectionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the metal connecting line with either the gate electrode of the second TFT or the source/drain electrode of the first TFT by providing them on the same layer. This integration eliminates the need for a separate connecting line while maintaining the electrical connection function, thereby reducing device complexity and simplifying the manufacturing process.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If a separate metal connecting line is provided, then the connection between TFTs is established, but excessive via-holes are required which reduces the aperture ratio

Engineering Contradiction:
Improveconnection reliabilityVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

By merging the connecting line with existing electrodes on the same layer, the patent eliminates the need for additional via-holes that would be required to connect separate metal layers. This reduces the number of via-holes and increases the aperture ratio of the display device.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If the metal connecting line is overlaid by insulating materials to avoid short-circuiting, then short-circuit prevention is achieved, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveshort-circuit preventionVSAvoidmanufacturing process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent combines the connecting line and gate electrode/source-drain electrode into a single structure on the same layer, eliminating the need for additional insulating material layers that would be required to isolate separate metal connecting lines. This simplifies the manufacturing process while still preventing short-circuits through proper spatial arrangement.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9484396B2Array substrate, method for manufacturing the same, display device and electronic product
Publication Date: 2016.11.01 BOE TECHNOLOGY GROUP CO LTD
  • US9484396B2 patent drawing
  • US9484396B2 patent drawing
  • US9484396B2 patent drawing

AI summary

The present disclosure provides an array substrate, including a plurality of sub-pixel regions arranged in a matrix form. Each sub-pixel region may at least include a first thin film transistor (TFT) and a second thin film transistor. The first thin film transistor may include a first gate electrode, a first source electrode and a first drain electrode. The second thin film transistor may include a second gate electrode, a second source electrode and a second drain electrode. The first gate electrode and at least one of the second source electrode and the second drain electrode may be provided on a same layer. The second gate electrode and at least one of the first source electrode and the first drain electrode may be provided on a same layer. The second gate electrode and the first source electrode may be integrated together.