Array Substrate Electrode Layout for Parasitic Capacitance Control
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Solution Overview
Problem
In the production of array substrates, unstable preparation processes and limited accuracy can lead to parasitic capacitors with varying capacitance values, reducing yield and quality.
Innovation Solution
The array substrate design includes specific configurations for the thin film transistor electrodes and gate lines, ensuring non-overlapping projections and adjusted distances to enhance preparation accuracy and reduce short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electrode and gate line configurations are used, then device complexity is reduced, but parasitic capacitors with varying capacitance values are generated, reducing yield and quality
Solution Approach 1:
The gate line is segmented into multiple sections (first gate line section, second gate line section, third gate line section) with different widths. The first and third sections have smaller widths while the second section has a larger width, allowing differential control of parasitic capacitance in different regions of the electrode structure
Solution Approach 2:
Different sections of the gate line are designed with locally optimized widths to match the specific capacitance requirements of underlying electrode portions. The wider second gate line section compensates for higher parasitic capacitance in central electrode regions, while narrower first and third sections are sufficient for edge regions
2Reliability
If electrode projections overlap with gate projections, then manufacturing is simplified, but short circuits are more likely to occur, reducing yield
Solution Approach 1:
The solution moves from two-dimensional planar overlap to three-dimensional stacked configuration. electrode projections are positioned in the same plane while gate line projections are in a different plane (vertical stacking), eliminating short circuit risk while maintaining electrical functionality through vertical field penetration
3Reliability
If uniform gate line width is used, then manufacturing is easier, but parasitic capacitance varies across different regions, reducing quality
Solution Approach 1:
The gate line is designed with non-uniform width where different sections have different widths tailored to local capacitance requirements. The first gate line section has width W1, the second section has width W2 (where W2 > W1), and the third section has width W3 (where W3 ≥ W1), creating locally optimized capacitance compensation throughout the structure
Data Source
AI summary
The present application provides an array substrate and a display panel. The array substrate includes a gate of a thin film transistor; a first electrode of the transistor, including a first body and a first end; a second electrode of the transistor, including a second body and a second end; orthographic projections of the first body and the second body being located in an orthographic projection of the gate, orthographic projections of at least partial area of the first end and at least partial area of the second end not overlapping with the orthographic projection of the gate, an orthographic projections of the first end and the second end being both located on the same side of the orthographic projection of the gate; in a first direction, an average distance from the first end to the second end is greater than that from the first body to the second body.