Array Substrate Electrode Protection Against Etching Corrosion

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Solution Overview

Problem

High pixel density in display devices, particularly in virtual reality products, leads to challenges in maintaining the integrity of electrodes during the manufacturing process, resulting in defects like dark spots due to over-etching and corrosion, which cause short circuits and fractures in the pixel and common electrodes.

Innovation Solution

The array substrate design includes a base substrate with a first electrode having a pad portion with intersecting surfaces, insulation layers with strategically formed via holes, and a second electrode connected through these holes, ensuring the second surface of the first electrode is in contact with the first insulation layer to protect against corrosion, and the manufacturing method involves precise formation of these layers to prevent recessing and fractures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the pixel density is increased to achieve high PPI display resolution, then the display resolution is improved, but the electrode structure becomes more susceptible to over-etching and corrosion during manufacturing

Engineering Contradiction:
Improvedisplay resolutionVSAvoidelectrode integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective insulation layer on the electrode surface before the etching process. This insulation layer is prepared in advance to prevent over-etching and corrosion of the electrode during subsequent manufacturing steps, thereby maintaining electrode integrity while enabling high PPI display resolution

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary substance (insulation layer) between the electrode and the etching environment. This intermediary layer acts as a mediator that protects the electrode from direct contact with corrosive etching solutions, preventing damage while allowing the etching process to proceed for pattern formation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the via hole size is increased to ensure proper electrical connection, then the electrical connection is improved, but the risk of electrode recessing and film layer fracture increases

Engineering Contradiction:
Improveelectrical connectionVSAvoidfilm layer integrity
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent applies preliminary action by forming the protective insulation layer before creating via holes. This pre-formed insulation layer protects the electrode edges during via hole etching, preventing electrode recessing that could lead to film layer fracture, while still allowing sufficient via hole size for reliable electrical connection

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements beforehand cushioning by providing the insulation layer as a protective buffer before the via hole formation process. This cushioning layer absorbs the mechanical and chemical stress during etching, preventing direct damage to the electrode and reducing the risk of film layer fracture

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11710747B2Array substrate, manufacturing method thereof, and display device
Publication Date: 2023.07.25 ORDOS YUANSHENG OPTOELECTRONICS
  • US11710747B2 patent drawing
  • US11710747B2 patent drawing
  • US11710747B2 patent drawing

AI summary

An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes: a base substrate; a first electrode located on the base substrate and including a pad portion, the pad portion including a first surface and a second surface, the second surface being closer to the base substrate than the first surface; a first insulation layer located on the first electrode and including a first via hole; a second insulation layer located on the first insulation layer and including a second via hole; and a second electrode located on the second insulation layer; the second electrode is electrically connected with the first electrode at the pad portion through the first via hole and the second via hole, and an orthographic projection of the pad portion on the base substrate falls within an orthographic projection of the second via hole on the base substrate.