Array Substrate Electrode Segmentation for Display Quality
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Solution Overview
Problem
Current array substrates for TFT-LCDs face issues with transmittance, luminance, contrast, and production costs due to differences in design structures and patterning processes between IPS and ADS display modes, leading to quality defects like greenish pictures and line image sticking, especially as panel size increases.
Innovation Solution
An array substrate design featuring pixel units with a first display electrode and a second display electrode, where the insulating portion includes via holes with perpendicular inner walls, allowing the electrodes to be formed on different planes without overlapping, thereby avoiding storage capacitance and simplifying the patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the array substrate uses ADS display mode with pixel electrode and common electrode arranged in upper and bottom layers, then the controllable area of electric field is wider and transmittance, luminance, and contrast are improved, but a large overlapping zone between electrodes forms causing storage capacitance that leads to quality defects like greenish pictures and line image sticking
Solution Approach 1:
The patent divides the display area into pixel regions and non-pixel regions, and segments the electrode arrangement accordingly. In pixel regions, the pixel electrode and common electrode are arranged in an upper-lower layer configuration to maintain wide electric field control. In non-pixel regions, the electrodes are arranged in the same plane to eliminate overlapping zones. This spatial segmentation resolves the contradiction by allowing the beneficial upper-lower arrangement only where needed for display performance while avoiding the harmful overlapping that causes quality defects.
Solution Approach 2:
The patent applies different electrode arrangement strategies in different spatial locations: in pixel regions, electrodes are arranged in upper and bottom layers to achieve wide electric field control and good display quality; in non-pixel regions, electrodes are arranged in the same plane to eliminate overlapping zones and avoid storage capacitance-related defects. This local differentiation of electrode configuration resolves the contradiction between achieving wide electric field control and avoiding quality defects.
2Area of stationary object
If the array substrate uses ADS display mode with pixel electrode and common electrode arranged in upper and bottom layers, then the controllable area of electric field is wider, but the production cost increases due to more complex patterning process
Solution Approach 1:
The patent merges the patterning of pixel electrodes and common electrodes into a single patterning process. By designing the electrode patterns such that they can be formed simultaneously in one exposure and development cycle, the complex multi-step patterning is simplified. This reduces manufacturing complexity and cost while maintaining the upper-lower layer electrode arrangement that provides wide electric field control.
3Ease of manufacture
If the array substrate uses IPS display mode with pixel electrode and common electrode arranged on the same plane, then the fabrication process is simpler with four-patterning, but the controllable area of electric field is limited resulting in lower transmittance, luminance, and contrast
Solution Approach 1:
The patent segments the substrate into pixel regions and non-pixel regions, applying different electrode arrangements in each. In pixel regions, the upper-lower layer arrangement is used to achieve wide electric field control and high luminance. In non-pixel regions, the same-plane arrangement is used to maintain simple fabrication processes. This spatial segmentation allows the system to achieve high performance where needed while keeping manufacturing simple overall.
Solution Approach 2:
The patent applies local quality by using different electrode configurations in different locations: upper-lower layer arrangement in pixel regions for high luminance and wide electric field control, and same-plane arrangement in non-pixel regions for manufacturing simplicity. This resolves the contradiction between fabrication simplicity and display performance by optimizing each region for its specific function.
Data Source
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Figure 3(a)~3(b)
Figure 3(c)~4(a)
AI summary
Embodiments of the invention provide an array substrate comprising a plurality of pixel units, each of the pixel units including a first display (e.g. pixel) electrode (311), a second display (e.g. common) electrode (312) and an insulating portion (304, 310), wherein the insulating portion (304,310) comprises a plurality of (e.g. strip-shaped) first via holes; the first display electrode (311) is disposed on the top surface of the insulating portion (310), and the second display electrode (312) is disposed at the bottom surfaces of the first via holes. Embodiments of the invention further provide methods for manufacturing the array substrate.