Array Substrate Vertical Electrode Stacking for Touch Displays
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Solution Overview
Problem
Current touch display technologies face challenges in manufacturing light and thin products while maintaining effective display and touch functions, particularly in reducing parasitic capacitance and power dissipation, and simplifying the manufacturing process.
Innovation Solution
The array substrate design includes thin film transistors, pixel electrodes, common electrodes, and touch electrodes, with an insulating planarization layer between the transistors and electrodes, optimizing electrode placement to increase storage capacitance and reduce parasitic capacitance, and using a protective layer to prevent decomposition during the sputtering process, thereby simplifying the manufacturing process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the common electrode is disposed below the pixel electrode and the touch electrode is disposed above the pixel electrode, then the manufacturing process is simplified, but the parasitic capacitance increases and power dissipation increases
Solution Approach 1:
The patent introduces a vertical stacking dimension to separate electrodes that would otherwise be planarly arranged. By disposing the common electrode, pixel electrode, and touch electrode in different vertical layers (common electrode below pixel electrode, touch electrode above pixel electrode), the patent reduces parasitic capacitance between electrodes while maintaining a simplified manufacturing process. This dimensional reorganization allows electrodes to be closer in vertical distance rather than horizontal distance, reducing capacitive coupling.
2Manufacturing precision
If the insulating planarization layer thickness is increased to improve planarity, then the manufacturing complexity increases, but the aperture ratio decreases
Solution Approach 1:
The patent optimizes the thickness parameter of the insulating planarization layer to balance planarity requirements with aperture ratio preservation. By carefully controlling the thickness within a specific range, the patent achieves sufficient planarity for subsequent electrode formation while minimizing the vertical space consumed, thereby maintaining a high aperture ratio for light transmission.
3Reliability
If the electrode arrangement is optimized to reduce parasitic capacitance, then the storage capacitance stability improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent uses vertical stacking to simplify the electrode arrangement while achieving reduced parasitic capacitance. Instead of complex lateral positioning adjustments, the patent achieves electrode separation through vertical layering, making the arrangement easier to manufacture while improving storage capacitance stability.
Solution Approach 2:
The insulating planarization layer serves as an intermediary between the common electrode and the pixel electrode, and between the pixel electrode and touch electrode. This intermediary layer provides electrical isolation that reduces parasitic capacitance while maintaining a relatively simple manufacturing process through standard thin-film deposition techniques.
Data Source
AI summary
An array substrate includes: thin film transistors disposed on a base substrate; pixel electrodes disposed on a side of the thin film transistors facing away from the base substrate, each pixel electrode being coupled with a drain of a corresponding thin film transistor; common electrodes disposed on a side of the pixel electrodes facing away from the thin film transistors; and touch electrodes disposed on a side of the common electrodes facing away from the pixel electrodes, each touch electrode being coupled with a corresponding common electrode.