Array Substrate Interconnect Layout for Electromigration Suppression
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Solution Overview
Problem
In display technologies, the increasing complexity of peripheral driving circuits leads to issues like electromigration, causing abnormal signal transmission and resulting in jitter horizontal stripes due to the presence of black dots between transistors and scan lines, which complicates the manufacturing process and reduces product yield.
Innovation Solution
The array substrate design includes a base with a first conductive layer, an insulating layer, and a second conductive layer, featuring via holes that connect electrodes of transistors in a shift register, thereby reducing the likelihood of electromigration by minimizing interconnection lengths and optimizing distances between conductive elements, such as the common electrode block and output signal line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the peripheral driving circuits are made more complex to increase pixel density and reduce frame width, then the display resolution and compactness are improved, but electromigration occurs causing black dots and abnormal signal transmission
Solution Approach 1:
The patent divides the conductive layer into multiple segments (first conductive layer, second conductive layer, third conductive layer) with insulating layers between them. This segmentation breaks the continuous conductive path into discrete segments, reducing the length of each segment and thereby suppressing electromigration while maintaining the necessary electrical connections for high pixel density circuits.
Solution Approach 2:
The patent introduces a vertical dimension by stacking multiple conductive layers at different heights (first, second, and third conductive layers separated by insulating layers). This three-dimensional arrangement allows signal transmission paths to be distributed across multiple layers, reducing the horizontal distance electrons must travel and thus suppressing electromigration in high-density circuit designs.
2Reliability
If the distance between conductive elements is reduced to minimize interconnection lengths, then electromigration is suppressed, but the manufacturing precision requirements increase
Solution Approach 1:
The conductive paths are segmented into multiple layers with insulating barriers between them. Each layer can be manufactured and aligned independently, allowing the use of standard manufacturing tolerances for each layer while achieving very short effective current path lengths through the stacked configuration, thus suppressing electromigration without requiring ultra-precise single-layer alignment.
Solution Approach 2:
Insulating layers are introduced as intermediary structures between adjacent conductive layers. These insulating layers provide physical separation and electrical isolation, allowing conductive elements in different layers to be positioned very close to each other (minimizing interconnection length) while preventing direct contact and short circuits, thereby enabling electromigration suppression with manageable manufacturing precision.
3Reliability
If multiple conductive layers with via holes are used to connect transistor electrodes, then the interconnection length is minimized suppressing electromigration, but the device structure becomes more complex
Solution Approach 1:
The patent segments the conductive system into multiple functional layers (first conductive layer for gate electrodes, second conductive layer for source/drain electrodes, third conductive layer for interconnections) separated by insulating layers with via holes. This segmentation allows each layer to have a specific function, reducing the need for long interconnections within single layers and suppressing electromigration while maintaining reasonable structural complexity through systematic layering.
Solution Approach 2:
The stacked conductive layer structure serves multiple functions simultaneously: it provides electrical connections between transistor electrodes, minimizes interconnection lengths to suppress electromigration, and maintains a systematic manufacturing process. The via holes serve dual purposes of electrical connection and structural alignment references, reducing overall device complexity despite the multiple layers.
Data Source
AI summary
An array substrate includes a base, a first conductive layer disposed at a side of the base, an insulating layer disposed at a side of the first conductive layer away from the base, and a second conductive layer disposed at a side of the insulating layer away from the first conductive layer. The insulating layer is provided with a first via hole exposing the first electrode of the first transistor and a second via hole exposing the first electrode of the second transistor. The second conductive layer includes a first conductive connection portion, and the first conductive connection portion connects the first electrode of the first transistor and the first electrode of the second transistor through the first via hole and the second via hole.