Array Substrate Pad Layer Configuration for ESD Protection
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Solution Overview
Problem
During the fabrication of array substrates, electrostatic discharge (ESD) between the gate line and the data line can cause short circuits, leading to defects such as split screens and full screen stripes in display panels, due to the accumulation of static electricity during the patterning process.
Innovation Solution
The introduction of a first active pad layer that overlaps with the gate line but is located outside the region where the gate and data lines intersect, along with a data line pad layer, to provide a channel for electrostatic discharge and reduce the likelihood of ESD occurring between the gate and data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the base substrate and array device are in friction or operate in vacuum wall during fabrication, then charges accumulate on the base substrate surface forming static electricity, but this leads to ESD discharge that damages film layers and causes short circuits
Solution Approach 1:
The patent introduces a first active pad layer as an intermediary component between the gate line and data line. This pad layer serves as a mediator that provides a controlled discharge path for static electricity, preventing uncontrolled ESD discharge from damaging the film layers and causing short circuits between the gate and data lines.
Solution Approach 2:
The patent converts the harmful static electricity accumulation into a beneficial controlled discharge mechanism. By designing the first active pad layer with specific geometric features (bent parts on extending parts), the static electricity is channeled through a predetermined path that protects the critical film layers while utilizing the electrostatic energy in a controlled manner.
2Reliability
If ESD discharge occurs between gate line and data line, then short circuit is caused, but this results in split screen and full screen stripes defects in display panel
Solution Approach 1:
The first active pad layer acts as an intermediary that intercepts and redirects the ESD discharge path. By positioning the pad layer to overlap with the gate line outside the gate-data line intersection region, it provides an alternative discharge route that prevents direct short circuiting between the gate and data lines, thereby avoiding display defects.
Solution Approach 2:
The patent implements preliminary protective action by pre-positioning the first active pad layer in the design stage. This pad layer is configured beforehand to intercept potential ESD discharge paths before they can cause damage to the film layers or create short circuits that would result in display defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the probability of short circuits between the gate and data lines due to ESD, thereby improving the yield and quality of the display panel by preventing defects like split screens and full screen stripes.
Implementation Method 1
charges accumulate on a surface of the base substrate, so as to form static electricity. When the charges accumulate to a certain extent, discharge, that is, Electro Static Discharge (ESD) occurs
Data Source
Figure 1a~1c
Figure 1d~2b
Figure 2c~3b
AI summary
An array substrate (200), a fabrication method of the array substrate (200), and a display panel and an electronic device having the array substrate (200) are provided. The array substrate (200) includes a base substrate (201), and a gate line (202), an insulating layer (204), a data line (208), and a first active pad layer (216) provided on the base substrate (201); wherein, the insulating layer (204) is provided on the gate line (202), the data line (208) is arranged on the gate line (202) through the insulating layer (204) and is arranged intersecting with the gate line (202), the first active pad layer (216) is arranged on the gate line (202) through the insulating layer (204) and is arranged overlapping with the gate line (202), and the first active pad layer (216) is arranged outside a region where the gate line (202) and the data line (208) overlap with each other.