Array Substrate Gate Connection Layout for ESD-Protected Pixels
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Solution Overview
Problem
In display panels, electrostatic charges generated during the dry etching process can cause breakdown between the gate and channel of transistors, leading to pixel failure and reduced panel yield.
Innovation Solution
The array substrate design includes connecting parts that bridge the gate and gate lines across different conductive layers, specifically through the source-drain and light shielding layers, preventing static electricity from reaching the transistor channels, thereby avoiding damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate line is directly connected to the gate in the same conductive layer, then the signal transmission is simple and direct, but electrostatic charges can reach the transistor channel causing breakdown and pixel failure
Solution Approach 1:
The patent transitions the connection from a two-dimensional same-layer configuration to a three-dimensional multi-layer configuration. The connecting part extends vertically through different conductive layers (gate line layer, interlayer dielectric, and gate layer) using vias to bridge the gap, thereby preventing electrostatic charges from reaching the transistor channel while maintaining electrical connection.
Solution Approach 2:
The connecting part acts as an intermediary structure between the gate line and the gate. It includes conductive components in different layers (first connecting part in gate line layer, second connecting part in gate layer) connected through vias, serving as a mediator that transmits signals while blocking electrostatic damage paths.
2Reliability
If multiple conductive layers and vias are used to connect gate line and gate, then electrostatic protection is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The connecting part is segmented into multiple functional components distributed across different layers: the first connecting part in the gate line layer, the interlayer dielectric with embedded vias, and the second connecting part in the gate layer. This segmentation allows each component to be optimized independently while collectively achieving electrostatic protection.
Solution Approach 2:
The structure employs a nested arrangement where the first connecting part and second connecting part are positioned at different vertical levels, with the interlayer dielectric and vias nested between them. The via structure itself is nested, with the conductive fill material nested within the etched via holes in the dielectric layers.
Data Source
AI summary
The present disclosure relates to an array substrate and a display panel, the array substrate including at least one pixel unit and a first gate line, each pixel unit including at least one sub-pixel, each sub-pixel including a pixel circuit, the pixel circuit including a first transistor, the first gate line being electrically connected to a gate of the first transistor through a first connecting part, the first connecting part and the first gate line being located in different conductive layers from each other. The array substrate provided in some embodiments of the present disclosure eliminates the risk of pixel circuit transistor damage caused by electrostatic conduction of the gate line by means of the measure of same layer separation and cross layer connection of the gate of the transistor and the corresponding gate line.