Array Substrate Via Offset Layout for ESD-Induced Short Prevention
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Solution Overview
Problem
Current array substrates and electronic devices suffer from shorts between common electrodes and pixel electrodes due to electrostatic discharge causing cracks in the passivation layer, leading to issues like dark spots or horizontal lines during lighting tests.
Innovation Solution
The array substrate design features a staggered or overlapping orthographic projection of via holes and electrodes, with a second insulating layer filling the recessed areas formed by the via holes, preventing cracks and potential shorts between the electrode layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the first via hole and second via hole are aligned vertically, then the manufacturing process is simpler, but electrostatic discharge causes cracks in the insulating layer leading to shorts between electrodes
Solution Approach 1:
The patent transitions from vertical alignment (1D) to staggered horizontal positioning (2D) of via holes. The first via hole connects the common signal line to the conductive electrode, while the second via hole is positioned laterally offset to connect the pixel electrode to the data signal line. This dimensional change eliminates the short circuit path while maintaining manufacturing feasibility through standard photolithography patterning.
Solution Approach 2:
The patent introduces asymmetric positioning where the second via hole is deliberately offset from the first via hole in the horizontal direction. This asymmetric arrangement breaks the vertical symmetry that causes electrostatic discharge-induced cracks, while the offset distance is optimized to prevent shorts between the common electrode and pixel electrode.
2Reliability
If the via holes are staggered horizontally, then shorts between electrodes are prevented, but the manufacturing precision requirements increase
Solution Approach 1:
The patent introduces a planarization layer as an intermediary between the first and second via holes. This planarization layer fills and flattens the surface irregularities created by the staggered via hole arrangement, providing a uniform baseline for subsequent electrode formation. This mediator reduces the precision requirements for via hole positioning by compensating for dimensional variations.
Solution Approach 2:
The patent performs preliminary planarization before forming the pixel electrode and data signal line. By pre-flattening the surface with the planarization layer, the subsequent manufacturing steps can proceed with relaxed precision requirements, as the critical alignment is already established in the underlying layers.
3Stability of the object's composition
If common signal lines are connected to common electrodes through via holes, then uniform signal distribution is achieved, but cracks form in the passivation layer causing display defects
Solution Approach 1:
The patent extracts the second via hole from the vertical alignment path of the first via hole, removing it from the high-stress region where electrostatic discharge concentrates. By laterally offsetting the second via hole, the patent eliminates the crack propagation path that would otherwise connect the common electrode to the pixel electrode through the passivation layer.
Data Source
AI summary
An array substrate and an electronic device are disclosed. The electronic device includes a display panel including an array substrate. The array substrate includes a first insulating layer provided with a plurality of first via holes, a second insulating layer provided with a plurality of second via holes, and a second electrode layer includes a second electrode. An orthographic projection of at least one of the second via hole or the second electrode on the substrate is staggered from an orthographic projection of the first via hole on the substrate, so that a short between the first electrode and the second electrode can be prevented.