Array Substrate Etch Stop Layer Wet Dry Etching Process
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Solution Overview
Problem
In array substrates using etch stop layer type bottom-gate low-temperature poly-silicon thin film transistors, the simultaneous dry etching of the etch stop layer and active layer results in equal pattern sizes due to similar etch selectivity ratios, limiting on-state current and electron mobility, and increasing the risk of over-etching and short circuits.
Innovation Solution
A manufacturing method involving a wet etching process for the etch stop layer and a dry etching process for the active layer, with the etch stop layer material having a high selectivity ratio to the semiconductor layer, allowing for a controlled etch stop layer and active layer formation with increased contact area between electrodes and reduced over-etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If simultaneous dry etching is used for both etch stop layer and active layer, then the manufacturing process is simplified, but the contact area between electrodes and active layer is reduced and over-etching risk increases
Solution Approach 1:
The patent divides the etching process into two separate stages: first performing wet etching to form the etch stop layer with precise pattern definition, then performing dry etching to form the active layer. This segmentation allows each etching process to be optimized independently, preventing the pattern size equality problem that occurs with simultaneous etching and ensuring proper contact area between electrodes and active layer.
Solution Approach 2:
The patent performs the wet etching of the etch stop layer as a preliminary action before the dry etching of the active layer. By establishing the etch stop layer pattern first with high precision wet etching, subsequent dry etching can proceed with proper pattern definition already in place, avoiding the over-etching and pattern distortion issues that occur when both layers are etched simultaneously.
2Reliability
If etch stop layer completely covers active layer, then back channel damage is prevented, but on-state current and electron mobility are limited
Solution Approach 1:
The patent applies local quality by making the etch stop layer coverage non-uniform: it completely covers the active layer in the channel region to prevent back channel damage, while leaving the source and drain regions exposed to allow proper electrode contact. This is achieved through selective wet etching that removes etch stop layer material from source/drain areas while maintaining coverage over the channel, thereby simultaneously achieving both back channel protection and adequate contact area.
3Device complexity
If same mask pattern is used for both etch stop layer and active layer, then masking process is simplified, but pattern size equality limits device performance
Solution Approach 1:
The patent changes the etching parameters between the two etching steps: using wet etching chemistry optimized for the etch stop layer material first, then using dry etching parameters optimized for the active layer material. This parameter change allows different pattern dimensions to be achieved from the same mask pattern, as the different etching mechanisms produce different etch rates and pattern profiles for the two materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances on-state current and electron mobility by increasing the contact area between electrodes and the active layer, while reducing the risk of short circuits and over-etching, thereby improving the yield rate of the product.
Implementation Method 1
subjecting the etch stop layer material to a wet etching process to form an etch stop layer
Implementation Method 2
subjecting the semiconductor layer to a dry etching process to form an active layer
Implementation Method 3
crystallizing the amorphous silicon layer to form the poly-silicon layer by a laser annealing process
Data Source
AI summary
A manufacturing method of an array substrate, an array substrate and a display device are disclosed. The manufacturing method of the array substrate includes: providing a base substrate (200); forming a semiconductor layer on the base substrate; depositing an etch stop layer material on the semiconductor layer; subjecting the etch stop layer material to a wet etching process to form an etch stop layer; subjecting the semiconductor layer to a dry etching process to form an active layer, wherein the active layer includes a first region and a second region surrounding the first region, an orthographic projection of the etch stop layer on the base substrate completely coincides with an orthographic projection of the first region of the active layer on the base substrate.