Array Substrate Fabrication Using Etch-Stopper for Polysilicon TFTs
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Solution Overview
Problem
The existing array substrates for flat panel displays, such as LCD and OELD devices, face issues with parasitic capacitance and mobility due to thickness differences in the active layer of thin-film transistors (TFTs) caused by fabrication processes, leading to degraded properties and increased production costs.
Innovation Solution
A method is introduced to fabricate array substrates using a solid phase crystallization process to convert intrinsic amorphous silicon into polycrystalline silicon, with an etch-stopper layer preventing active layer damage during processing, reducing parasitic capacitance and improving mobility by optimizing the TFT structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional fabrication process is used to form the active layer, then the manufacturing process is simple, but the active layer thickness is non-uniform which degrades TFT properties
Solution Approach 1:
An etch-stopper layer is formed on the substrate before forming the active layer. This preliminary action prevents the active layer from being etched away during subsequent processing steps, ensuring uniform thickness and preventing degradation of TFT properties while maintaining a manageable fabrication process
Solution Approach 2:
The fabrication process is segmented into distinct stages with the etch-stopper layer serving as a protective barrier. This segmentation allows the active layer to be formed and processed independently without fear of damage, improving thickness uniformity without significantly increasing overall process complexity
2Object-generated harmful factors
If the active layer is made thinner to reduce parasitic capacitance, then parasitic capacitance is reduced, but the mobility property of TFT is degraded
Solution Approach 1:
The etch-stopper layer is strategically positioned only in regions where the active layer is vulnerable to etching damage. This local protection allows the active layer to be optimized for low parasitic capacitance in contact regions while maintaining sufficient thickness and mobility in the channel region where performance is critical
Solution Approach 2:
The etch-stopper layer acts as an intermediary protective barrier between the active layer and the etching process. It enables the use of thinner active layers to reduce parasitic capacitance while preventing etching damage that would otherwise degrade mobility, thus mediating between the two conflicting requirements
3Reliability
If polycrystalline silicon is used for the active layer to improve mobility, then TFT mobility is improved, but the fabrication process complexity and cost increase
Solution Approach 1:
The etch-stopper layer enables the use of polycrystalline silicon for the active layer by protecting it from etching damage during processing. This allows the fabrication process to achieve high mobility with polycrystalline silicon without requiring additional complex process steps, as the etch-stopper provides the necessary protection during standard processing
Solution Approach 2:
The etch-stopper layer is formed in advance before the polycrystalline silicon active layer is created. This preliminary protective measure enables the use of higher-mobility polycrystalline silicon material and processing methods without incurring additional complexity, as the protection is already in place during critical processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the mobility and reliability of TFTs, reduces production costs, and minimizes parasitic capacitance, thereby improving the overall performance of array substrates for flat panel displays.
Implementation Method 1
A method is introduced to fabricate array substrates using a solid phase crystallization process to convert intrinsic amorphous silicon into polycrystalline silicon
Data Source
AI summary
A method of fabricating an array substrate including forming a first metal layer; forming a gate insulating layer and an active layer; forming a second metal layer; forming a gate line, an etch-stopper and a gate electrode by patterning the first and second metal layers; forming an interlayer insulating layer including an opening, wherein the opening corresponds to the etch-stopper such that the opening is divided into first and second semiconductor contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact layers, a source electrode, a drain electrode and a data line, the first and second ohmic contact layers respectively contacting both sides of the active layer through the first and second semiconductor contact holes; removing an exposed portion of the etch-stopper; and forming a pixel electrode contacting the drain electrode.