Array Substrate Etching for Leakage Current and Line Breakage
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Solution Overview
Problem
In display devices, particularly those with inverted staggered TFT structures, excessive active semiconductor tail lengths lead to leakage current and small line widths result in line breakage risks during etching treatments, affecting safety, energy efficiency, and normal operation.
Innovation Solution
A manufacturing method for array substrates involving multiple etching and ashing treatments to reduce edge lengths of amorphous silicon and ohmic contact layers, using specific etching solutions and masks to control layer dimensions and shapes, including the use of aluminum and molybdenum layers, to minimize leakage current and line breakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the active semiconductor layer is extended to ensure complete coverage of the metal layer, then the switching function is improved, but the leakage current increases due to excessive tail length
Solution Approach 1:
The patent applies different etching rates to different regions of the active semiconductor layer. The channel region is etched at a slower rate to maintain proper switching function, while the tail region is etched at a faster rate to reduce leakage current. This is achieved by controlling the etching process parameters to create selective removal rates across the layer.
Solution Approach 2:
The etching process is segmented into multiple stages with different conditions. The first etching step removes the photoresist layer and begins removing the active semiconductor layer, while the second etching step continues the removal but with controlled parameters to prevent excessive tail length. This segmentation allows different regions to be treated differently.
2Manufacturing precision
If the source/drain electrode line width is reduced to achieve higher resolution, then the display resolution is improved, but the risk of line breakage increases during etching
Solution Approach 1:
The patent forms a protective layer on the source/drain electrodes before the etching process. This protective layer is deposited in advance to prevent the thin electrode lines from breaking during the subsequent etching operations. The protective layer acts as a mechanical support structure that maintains line integrity throughout the manufacturing process.
Solution Approach 2:
The protective layer serves as a cushioning structure that absorbs the mechanical stress and chemical attacks during etching. By providing this protective barrier beforehand, the patent prevents line breakage without compromising the final electrode dimensions or the display resolution.
3Manufacturing precision
If multiple etching steps are performed to precisely control layer dimensions, then the manufacturing precision is improved, but the process complexity increases
Solution Approach 1:
The patent uses a single etching process that performs multiple functions: removing the photoresist layer, defining the active semiconductor pattern, and controlling the tail length. By designing the etching solution and process parameters to achieve multiple objectives in one step, the patent reduces process complexity while maintaining manufacturing precision.
Solution Approach 2:
The patent combines the photoresist removal and active semiconductor layer etching into a single etching step. The etching solution is formulated to selectively remove both materials with appropriate rates, merging two operations into one and simplifying the overall process while maintaining precise dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces leakage current and line breakage risks, ensuring safe and energy-efficient operation by precisely controlling layer dimensions and shapes through a combination of wet and dry etching with ashing treatments.
Implementation Method 1
performing a first wet etching on the active switches; performing a second wet etching on the active switches
Implementation Method 2
performing a first dry etching on the active switches; performing a second dry etching on the active switches
Implementation Method 3
performing a first ashing treatment on the photoresist layer; performing a second ashing treatment on the photoresist layer
Data Source
AI summary
An array substrate and a manufacturing method thereof are provided. The manufacturing method includes steps of: providing a first substrate; providing a first mask and arranging active switches on the first substrate; providing a second mask, forming a photoresist layer on the active switches and sequentially performing following steps of: performing a first wet etching on the active switches, performing a first ashing treatment on the photoresist layer, performing a first dry etching on the active switches, performing a second wet etching on the active switches, performing a second ashing treatment on the photoresist layer and performing a second dry etching on the active switches; providing a third mask and forming a protective layer on a metal layer of the active switches; and providing a fourth mask and forming a pixel electrode layer on the protective layer.