Array Substrate Fabrication via Solid Phase Crystallization
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Solution Overview
Problem
The existing array substrates for flat panel displays, particularly in LCD and OELD devices, face issues due to thickness variations in the active layer of TFTs, leading to degraded properties and increased production costs, as well as instability under light or electric fields, and require complex doping processes for polycrystalline silicon TFTs.
Innovation Solution
A method is developed to fabricate an array substrate by forming a first metal layer, an inorganic insulating layer, and crystallizing intrinsic amorphous silicon into polycrystalline silicon before patterning, minimizing thermal deformation and avoiding dry-etching, which maintains uniform active layer thickness and improves mobility, using a solid phase crystallization process and specific masking techniques to form TFTs with uniform thickness and improved stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the active layer thickness is varied to form source and drain regions, then the TFT switching characteristics are improved, but the manufacturing precision and uniformity of the active layer are degraded
Solution Approach 1:
The patent applies local quality by forming different thickness regions of the active layer at specific locations. The active layer has a first thickness in the channel formation region and a second thickness (greater than the first) in the source/drain contact regions. This localized thickness variation improves carrier injection at source/drain contacts while maintaining uniform thickness in the channel region for consistent switching characteristics.
Solution Approach 2:
The patent uses preliminary action by forming the active layer with varying thickness before the crystallization process. The amorphous silicon layer is deposited with different thicknesses in different regions, then selectively crystallized. This preliminary thickness configuration is preserved through the crystallization process, achieving the desired thickness profile without requiring post-crystallization etching that would compromise uniformity.
2Reliability
If polycrystalline silicon is used for the active layer to improve mobility, then the TFT performance is enhanced, but the device complexity and production cost increase due to required doping processes
Solution Approach 1:
The patent extracts the doping step from the conventional polycrystalline silicon TFT fabrication process. Instead of forming polycrystalline silicon and then doping it separately, the invention uses amorphous silicon that is crystallized in-situ during the TFT formation process. The amorphous silicon layer is deposited and then crystallized by heating, eliminating the need for separate doping processes while achieving comparable or superior electrical characteristics.
Solution Approach 2:
The patent substitutes the mechanical/chemical doping process with a thermal crystallization process. Instead of introducing dopants through ion implantation or diffusion, the invention relies on thermal energy to crystallize the amorphous silicon, creating an intrinsic or lightly-doped polycrystalline structure that achieves high mobility without complex doping equipment and processes.
3Productivity
If conventional fabrication processes are used, then the production time is reduced, but the active layer thickness uniformity and TFT properties are degraded
Solution Approach 1:
The patent merges the active layer formation and crystallization steps into a single integrated process. The amorphous silicon layer is deposited and then crystallized in-situ during the same fabrication sequence, eliminating separate etching and re-deposition steps required in conventional processes. This integration maintains thickness uniformity while reducing overall production time.
Solution Approach 2:
The patent uses an intermediary approach by employing an amorphous silicon layer as a precursor that is subsequently crystallized. The amorphous silicon serves as an intermediate state that can be easily deposited with uniform thickness, then transformed into polycrystalline silicon through thermal processing. This intermediary step enables precise thickness control while achieving the desired crystalline structure for high-performance TFTs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces production costs and time, maintains uniform active layer thickness, enhances TFT properties, and prevents degradation, while ensuring stability under light and electric fields, thus improving the performance and reliability of array substrates for flat panel displays.
Implementation Method 1
crystallizing the intrinsic amorphous silicon into an intrinsic polycrystalline silicon layer
Implementation Method 2
minimizing thermal deformation
Data Source
AI summary
A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.