Array Substrate Fan-Out Region Photomask Reduction
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Solution Overview
Problem
The increasing demand for reduced peripheral regions in display panels necessitates more conductive layers, leading to higher manufacturing costs due to the increased number of photomasks required.
Innovation Solution
A manufacturing method for array substrates that forms multiple fan-out lines using fewer photomasks by employing a half-tone photomask to simultaneously pattern the first conductive layer and the third metal layer, reducing the overall number of photomasks needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If more conductive layers are formed to adapt to reduced peripheral region, then the display panel can have reduced peripheral area, but the manufacturing cost increases due to more photomasks required
Solution Approach 1:
The patent combines the patterning of the third fan-out line and the common electrode into a single photomask process. The photomask simultaneously defines both the third fan-out line in the fan-out region and the common electrode in the pixel region, eliminating the need for separate photomasks and reducing manufacturing cost while maintaining the multi-layer conductive structure
Solution Approach 2:
The photomask is designed to serve multiple functions: it patterns not only the third fan-out line but also the common electrode, and works in conjunction with previous photomasks that formed first and second fan-out lines. This multi-functional approach reduces the total number of photomasks needed while achieving the reduced peripheral region design
2Device complexity
If more photomasks are used to form additional conductive layers, then the fan-out region can be optimized with multiple stacked lines, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the patterning steps for the third fan-out line and common electrode into a single photomask exposure and development process. This consolidation maintains the complex stacked conductive layer structure (first fan-out line, second fan-out line, and third fan-out line with transparent and auxiliary conductive layers) while reducing the number of separate photomask operations required
Data Source
AI summary
A manufacturing method of an array substrate including following steps is provided. A plurality of scan lines are formed on a substrate having a pixel region and a fan-out region. A plurality of data lines are formed. A plurality of transistors are formed and respectively electrically connected to the corresponding scan lines and data lines. A plurality of common electrodes are formed. A plurality of pixel electrodes are formed and respectively electrically connected to the corresponding transistors. A plurality of first fan-out lines, second fan-out lines, and third fan-out lines are formed in the fan-out region. Each of the third fan-out lines includes a transparent conductive layer and an auxiliary conductive layer located on and contacting the transparent conductive layer. The third fan-out lines and the common electrodes are formed by the same photomask.