Array Substrate Feedback Signal Lines for Common Voltage Compensation
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Solution Overview
Problem
In large-size displays with narrow bezels, signal line resistance increases, leading to signal distortion and image sticking due to high resolution and coupling capacitance, affecting normal pixel charging and discharging.
Innovation Solution
An array substrate with a common electrode, first, second, and third common signal lines, and feedback signal lines that transmit compensation voltage signals to the circuit board, reducing signal delay and distortion by compensating for common voltage signals across different regions of the display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the display size is increased with narrow bezels, then the display area is enlarged, but the signal line resistance increases causing signal distortion
Solution Approach 1:
The common electrode is divided into multiple regions (distal, proximal, middle) with separate common signal lines (first, second, third common signal lines) connecting to different regions. This segmentation allows independent voltage control for each region, compensating for signal degradation in different areas of the large display panel.
Solution Approach 2:
Different regions of the common electrode are provided with locally optimized signal lines and feedback mechanisms. The distal region receives feedback through dedicated feedback signal lines and connecting leads, while other regions have their own signal line configurations, allowing localized compensation for resistance and capacitance variations.
2Manufacturing precision
If high resolution is implemented, then the display quality is improved, but the coupling capacitance increases causing image sticking
Solution Approach 1:
Feedback signal lines are introduced to detect the actual voltage at the common electrode, particularly in the distal region. The feedback voltage is transmitted through connecting leads to control circuits that generate compensation signals, creating a closed-loop system that actively corrects for capacitance-induced voltage deviations and prevents image sticking.
Solution Approach 2:
The system dynamically adjusts the common voltage signal parameters based on feedback information. Compensation signals are generated to counteract the effects of coupling capacitance, changing the voltage parameters in real-time to maintain proper pixel charging and discharging characteristics despite high resolution requirements.
3Area of stationary object
If the signal line length is increased to cover large display areas, then the coverage is improved, but the signal delay increases
Solution Approach 1:
The display area is segmented into multiple zones served by different common signal lines of varying lengths. Shorter signal lines serve regions closer to the bonding region, while longer lines with compensation mechanisms serve distal regions, optimizing the balance between coverage and signal delay for each segment.
Solution Approach 2:
Compensation signals are generated in advance based on feedback information before being applied to the common electrode. This preliminary action anticipates and corrects for signal delays, ensuring that voltage compensation is already in place before display issues can manifest.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces signal delay and distortion, improving display quality by quickly transmitting compensation voltage signals to the common electrode, thereby preventing image sticking and enhancing the overall display effect.
Implementation Method 1
a feedback signal line configured to transmit a common voltage signal of the portion of the common electrode located in the distal region
Data Source
AI summary
An array substrate has a display area and a bonding region. The display area includes a distal region, a proximal region, and a middle region therebetween. The array substrate includes a base, a common electrode located in the display area, a connecting lead disposed outside the distal region, a conductive frame at least partially surrounding the display area, and at least one first common signal line, at least one second common signal line and at least one third common signal line. The first common signal line, the second common signal line and the third common signal line are respectively coupled to portions of the common electrode located in the distal region, the proximal region and the middle region. The first common signal line is coupled to the connecting lead. The connecting lead and the portion of the common electrode located in the distal region are coupled to the conductive frame.