Array Substrate Five-Mask Process for AD-SDS Displays

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Solution Overview

Problem

Conventional Advanced-Super Dimensional Switching (AD-SDS) liquid crystal display manufacturing methods require a six-mask process, leading to low manufacturing efficiency and high costs due to the complexity and time-consuming nature of the staggered back channel etching method.

Innovation Solution

A five-mask process method for manufacturing an array substrate, involving the formation of an inorganic material protrusion, reflective region pattern, gate and common electrodes, active island, data line, source and drain electrodes, planarization layer, and pixel electrode, which reduces the number of mask processes and manufacturing time, allowing for a co-planar pixel electrode formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a six-mask process is used for manufacturing AD-SDS display devices, then the manufacturing precision and structural complexity are maintained, but the productivity decreases and manufacturing time increases

Engineering Contradiction:
Improvestructural complexityVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent combines multiple patterning operations into a single mask process by forming the pixel electrode pattern, common electrode pattern, and gate electrode pattern simultaneously using one mask layer, thereby reducing the total number of mask processes from six to five while maintaining the required structural precision

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The mask layer serves multiple functions by simultaneously defining the pixel electrode, common electrode, and gate electrode patterns in a single process step, making the mask process multi-functional and eliminating the need for separate patterning steps for each electrode

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If a six-mask process is used for manufacturing AD-SDS display devices, then the manufacturing precision is maintained, but the manufacturing cost increases

Engineering Contradiction:
Improvestructural complexityVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent merges multiple patterning operations into a single mask process, reducing the number of mask layers and etching steps required, which directly lowers material costs and processing costs while maintaining the precision of electrode pattern formation

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If a five-mask process is used for manufacturing array substrates, then the productivity increases and manufacturing time decreases, but the manufacturing precision may be compromised

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidelectrode pattern accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary planning of the mask pattern design to ensure that a single mask process can accurately define multiple electrode patterns simultaneously, pre-calculating the optimal mask geometry and etching parameters to maintain precision while reducing process steps

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent optimizes etching parameters and mask material properties to achieve precise pattern formation in a reduced number of steps, adjusting process parameters such as etch selectivity, mask thickness, and development conditions to compensate for the simplified process

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9122114B2Array substrate and manufacturing method thereof
Publication Date: 2015.09.01 BOE TECHNOLOGY GROUP CO LTD
  • US9122114B2 patent drawing
  • US9122114B2 patent drawing
  • US9122114B2 patent drawing

AI summary

An embodiment of the disclosed technology provides a method of manufacturing an array substrate, including: a first mask process of forming an inorganic material protrusion on a base substrate; a second mask process of forming a reflective region pattern, a gate line, a gate electrode branched from the gate line, and a common electrode; a third mask process of forming an active island and a data line formed and forming a source electrode connected to the data line and a drain electrode on the active island and a channel; a fourth mask process of forming an insulation material layer, treating the insulation material layer to form a planarization layer, and forming a through hole above the drain electrode; and a fifth mask process of forming a pixel electrode and connected to the drain electrode via the through hole in a reflective region.