Array Substrate TFTs With Folded Channels for Higher Pixel Density
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Solution Overview
Problem
The challenge of reducing the size of thin film transistors in array substrates limits the improvement of pixel density in display panels, as the effective conductive channel length is determined by the horizontal distance between the source and drain.
Innovation Solution
The array substrate design includes a first and second conductor portion with a doped portion and channel portion arranged in different layers, reducing the channel length parallel to the substrate, and incorporating a gate positioned away from the doped portions to minimize transistor width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the channel length is reduced to increase pixel density, then the transistor size decreases, but the manufacturing precision and reliability become more difficult to control
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional folded channel structure. The channel is folded back on itself, creating vertical stacking that reduces the horizontal footprint while maintaining sufficient channel length for reliable operation. This dimensional change allows pixel density improvement without sacrificing manufacturing precision.
Solution Approach 2:
The folded channel structure nests the channel path within a compact footprint by having the channel fold back on itself. The source and drain regions are positioned closer together horizontally while the channel path length is maintained through vertical folding, effectively nesting the channel geometry within a smaller planar area.
2Area of moving object
If the transistor size is reduced to increase pixel density, then more pixels fit per inch, but the leakage current and hot carrier effects increase
Solution Approach 1:
By folding the channel in three dimensions, the patent maintains an adequate channel length (L) that provides sufficient electrical isolation between source and drain, reducing leakage current. The vertical folding preserves the channel length needed to suppress hot carrier effects while achieving compact horizontal dimensions for high pixel density.
Solution Approach 2:
The folded channel structure creates different local regions within the transistor - the folded sections provide extended channel length for reduced leakage, while the overall compact footprint achieves high pixel density. Each local region of the channel serves the specific function of maintaining electrical control while minimizing parasitic effects.
3Length of moving object
If the channel length is reduced horizontally, then the transistor width decreases, but the effective conductive channel length becomes insufficient
Solution Approach 1:
The patent compensates for reduced horizontal channel length by extending the channel in the vertical dimension through folding. The channel path folds back on itself, creating a longer effective conductive path within a compact horizontal footprint, thereby maintaining reliability while achieving smaller transistor size.
Solution Approach 2:
The folded channel structure dynamically adapts the channel path to fit within compact pixel areas while maintaining sufficient conductive length. The channel geometry is configured to fold and stack vertically, allowing the effective channel length to be maintained even as the horizontal dimensions are reduced for higher pixel density.
Data Source
AI summary
An array substrate and a display panel are disclosed. The array substrate includes a substrate, a first conductor portion located at a side of the substrate, a second conductor portion, and an active layer. The active layer includes a first doped portion, a second doped portion and a channel portion, the second doped portion is located at a side of the first doped portion away from the substrate, the channel portion is connected between the first doped portion and the second doped portion, the first conductor portion is contact with the first doped portion, and the second conductor portion is contact with the second doped portion.