Array Substrate Bonding Pin Layout for Reliable FPC Bonding
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Solution Overview
Problem
The reliability of the bonding effect between an existing Mini-LED substrate and an FPC (Flexible Printed Circuit) is low due to overlapping areas between insulating layers and bonding pins in the thickness direction of the substrate.
Innovation Solution
The array substrate design includes a bonding area with bonding pins, where the first insulating layer has openings that cover the orthographic projections of the bonding pins, preventing overlap and increasing the contact area between conductive particles and bonding pins, thereby enhancing the bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If insulating layers are placed over bonding pins in the thickness direction, then electrical insulation is improved, but bonding reliability deteriorates due to reduced contact area
Solution Approach 1:
The patent resolves the contradiction by transitioning from a vertical stacking arrangement (insulating layer completely covering bonding pin in thickness direction) to a lateral separation arrangement (insulating layer offset from bonding pin projection). This dimensional change eliminates the overlap between insulating layers and bonding pins in the thickness direction, ensuring full contact area for bonding while maintaining electrical insulation through proper lateral positioning of the insulating layer.
Solution Approach 2:
The bonding pin structure is segmented into multiple conductive portions (first conductive portion and second conductive portion) at different locations. The insulating layer is positioned to cover areas between these segments rather than overlying them, allowing each conductive portion to maintain its bonding functionality while the insulating layer provides electrical isolation in the gaps.
2Ease of manufacture
If insulating layers overlap bonding pins in the thickness direction, then manufacturing simplicity is improved, but bonding contact area is reduced
Solution Approach 1:
Instead of solving the contact area problem by reducing insulating layer thickness in the vertical dimension, the patent uses lateral positioning (another dimension) to achieve both goals: the insulating layer maintains its full thickness for manufacturing simplicity while being offset laterally so its projection does not cover the bonding pin, thus preserving maximum bonding contact area.
3Object-affected harmful factors
If multiple conductive layers with insulating layers between them are used, then electrical isolation is improved, but structural offset in bonding area increases
Solution Approach 1:
The patent applies local quality by positioning the insulating layer specifically in regions where electrical isolation is needed (between conductive traces) while deliberately creating offset from bonding pin locations. This localized positioning strategy ensures electrical isolation is provided exactly where required without introducing structural offset at the bonding area, maintaining manufacturing precision for bonding operations.
Data Source
AI summary
An array substrate (100) and a display device. The array substrate (100) includes a bonding area (102). The array substrate (100) includes a substrate (10), a first conductive layer (20) on the substrate (10), a first insulating layer (30) on one side of the first conductive layer (20) away from the substrate (10), and a second conductive layer (40) on one side of the first insulating layer (30) away from the substrate (10). The bonding area (102) is provided with bonding pins (201), and the bonding pin (201) includes a first conductive portion (21) and a second conductive portion (41) located on the side of the first conductive portion (21) away from the substrate (10), the first conductive portion (21) is located in the first conductive layer (20), the second conductive portion (41) is located in the second conductive layer (40), and the first conductive portion (21) is in direct contact with the second conductive portion (41). The first insulating layer (30) is provided with at least one first opening (301), and the orthographic projection of each of the first openings (301) on the substrate (10) covers the orthographic projections of the plurality of bonding pins (201) on the substrate (10).