Array Substrate Masking via Gate Electrode Alignment
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Solution Overview
Problem
The conventional manufacturing process of array substrates for liquid crystal display products is complex and costly due to the need for multiple mask plates and processes like film forming, exposing, and etching, which increases process complexity and cost.
Innovation Solution
A method where the gate electrode layer serves as a mask for forming the semiconductor layer, eliminating the need for additional mask plates and simplifying the process by aligning the semiconductor and gate electrode layers automatically, and forming through holes in the etching stop layer to connect source and drain electrodes with the semiconductor layer, thereby reducing the number of process steps and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing process with multiple mask plates is used, then film forming, exposing and etching can be completed, but process complexity and cost increase
Solution Approach 1:
The patent merges the functions of multiple mask plates into a single mask plate that simultaneously defines patterns for the gate electrode layer, semiconductor layer, source electrode layer, and drain electrode layer. This consolidation reduces the number of separate masking operations from multiple steps to a single integrated step, thereby simplifying the overall manufacturing process while maintaining precise alignment through the unified mask design.
Solution Approach 2:
The single mask plate performs multiple functions that previously required separate mask plates: it defines the gate electrode pattern, semiconductor layer pattern, source electrode pattern, and drain electrode pattern. This multi-functional mask plate eliminates the need for separate masking operations for each layer, reducing process complexity while ensuring consistent alignment across all layers through its universal patterning capability.
2Manufacturing precision
If multiple mask plates are used for each film layer, then precise patterning can be achieved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple separate mask plates into one integrated mask plate that accomplishes all patterning operations in a single step. This merging eliminates the need to manufacture, handle, and align multiple separate mask plates, thereby reducing manufacturing costs while maintaining patterning precision through the unified design of the single mask plate that defines all layer patterns simultaneously.
Solution Approach 2:
The single mask plate contains replicated pattern elements for different layers (gate electrode, semiconductor, source electrode, drain electrode) that are copied onto their respective layers through a single masking operation. This copying approach eliminates the need to create and use separate physical mask plates for each layer, reducing manufacturing costs while ensuring consistent pattern transfer across all layers.
3Manufacturing precision
If multiple exposing and etching steps are performed, then complete film formation is achieved, but process time increases
Solution Approach 1:
The patent merges multiple separate exposing and etching steps into a single integrated operation using one mask plate. Instead of performing exposing and etching for the gate electrode, then repeating for the semiconductor layer, source electrode, and drain electrode separately, the unified mask plate enables all layers to be patterned in one exposing and etching cycle, significantly reducing process time while maintaining complete and precise film formation across all layers.
Data Source
AI summary
A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on one side of a substrate, a gate electrode layer, a gate insulation layer and a semiconductor layer, wherein the gate electrode layer has a same pattern as the semiconductor layer; forming an etching stop layer on the semiconductor layer; forming a first, second hole and third through holes by patterning the etching stop layer; forming a source electrode layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; forming an active layer by etching the semiconductor layer at the location corresponding to the third through hole.