Array Substrate Gate Line End Capacitor for Static Discharge
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Solution Overview
Problem
In display product manufacturing, static electricity accumulated on gate lines in a GOA structure is not effectively discharged, leading to damage of GOA units and reduced yield due to point discharge.
Innovation Solution
A method involving forming independent first metal layer patterns with ends in non-display regions, an insulating layer, and a semiconductor pattern opposite to these ends, which forms a capacitor when heated, reducing voltage levels and preventing point discharge by enhancing electrical conductivity and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate lines are made as separate metal lines without connection to other components before depositing source/drain metal layer, then the manufacturing process is simplified, but static electricity accumulates on gate lines and causes point discharge that damages GOA units
Solution Approach 1:
The patent applies preliminary action by forming a semiconductor pattern on the insulating layer before depositing the source/drain metal layer. This semiconductor pattern is positioned to overlap with the gate line end in the non-display region, creating a capacitor structure in advance that will discharge static electricity before it can damage the GOA unit. The semiconductor layer is formed using a single patterning process along with the active layer, preparing the electrostatic protection structure beforehand.
Solution Approach 2:
The patent introduces an intermediary element - the semiconductor pattern - that acts as a mediator between the gate line and the GOA unit. This semiconductor pattern, positioned on the insulating layer and overlapping the gate line end, serves as an intermediate capacitor structure that captures and discharges static electricity, preventing direct damage to the GOA unit while maintaining the simplified gate line structure.
2Reliability
If the end of the gate line is made wider, then the capacitor effect is enhanced for better static electricity discharge, but the manufacturing precision requirements increase
Solution Approach 1:
The patent merges the formation of the semiconductor pattern with the active layer formation into a single patterning process. The semiconductor pattern and the TFT active layer are formed simultaneously using the same patterning step, which eliminates the need for separate alignment processes. This merging of operations reduces the cumulative alignment errors that would otherwise occur with multiple sequential patterning steps, thereby reducing manufacturing precision requirements while still achieving the enhanced capacitor effect through the wider gate line end.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces damage to GOA units by lowering voltage levels and preventing point discharge, thereby improving the yield of display products by utilizing the enhanced conductivity and capacitance of the semiconductor pattern.
Implementation Method 1
forming a semiconductor pattern on the insulating layer, a portion of semiconductor pattern is disposed directly opposite to the end... forms a capacitor when heated, reducing voltage levels and preventing point discharge by enhancing electrical conductivity and capacitance
Implementation Method 2
heating the base substrate on which the semiconductor pattern is formed... enhancing electrical conductivity and capacitance
Data Source
AI summary
A method for manufacturing an array substrate, including: forming a plurality of first metal layer patterns on a base substrate which are independent from each other, each of the plurality of first metal layer patterns including an end at a non-display region of the array substrate; forming an insulating layer on the plurality of first metal layer patterns; and forming a semiconductor pattern on the insulating layer, a portion of semiconductor pattern is disposed directly opposite to the end of the first metal layer patterns.