Array Substrate Gate Driving Layout for Uniform Display Brightness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display technologies face challenges in achieving uniform display brightness and narrow bezel designs due to resistance-capacitance (RC) loading in scanning signal lines, which results in insufficient charging time for sub-pixels and uneven display quality.
Innovation Solution
The array substrate design includes multiple groups of shift register circuits disposed in a non-edge region of the display area, with scanning signal lines extending along intersecting directions, and fan-out structures on the second surface to distribute signal connection lines, reducing RC loading and optimizing signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shift register circuits are disposed only in edge regions, then signal transmission is simplified, but display brightness uniformity deteriorates due to insufficient charging time in non-edge regions
Solution Approach 1:
The patent divides the display area into multiple regions and places shift register circuits in both edge and non-edge regions. This segmentation allows different regions to have appropriate driving circuits, ensuring uniform charging time and display brightness across the entire display area while maintaining manageable signal transmission complexity.
Solution Approach 2:
The patent applies local quality by positioning shift register circuits specifically in non-edge regions where they are most needed for uniform charging. This localized placement ensures that non-edge regions receive adequate driving signals without unnecessarily complicating the entire signal transmission structure.
2Illumination intensity
If multiple groups of shift register circuits are disposed in non-edge regions, then display brightness uniformity is improved, but device complexity increases
Solution Approach 1:
The patent segments the display area into multiple regions and places shift register circuits in both edge and non-edge regions. This segmentation allows different regions to have appropriate driving circuits, ensuring uniform charging time and display brightness across the entire display area while maintaining manageable signal transmission complexity.
Solution Approach 2:
The patent utilizes the second surface of the base substrate to dispose fan-out structures, effectively using three-dimensional space. This dimensional approach allows multiple groups of shift register circuits to be arranged in non-edge regions without proportionally increasing planar complexity, as circuits can be distributed across multiple surfaces and layers.
3Reliability
If scanning signal lines are extended to cover entire display area, then signal distribution is improved, but RC loading increases causing brightness non-uniformity
Solution Approach 1:
The patent divides the display area into multiple regions and places shift register circuits in both edge and non-edge regions. This segmentation allows different regions to have appropriate driving circuits, ensuring uniform charging time and display brightness across the entire display area while maintaining manageable signal transmission complexity.
Solution Approach 2:
The patent introduces fan-out structures as intermediaries between shift register circuits and scanning signal lines. These fan-out structures act as signal distributors that reduce RC loading effects by providing multiple parallel signal paths, thereby improving signal distribution uniformity without excessive line extension.
Data Source
AI summary
An array substrate includes a base substrate including a first surface and a second surface, scanning signal lines disposed on the first surface, at least two groups of shift register circuits disposed in a display area of the first surface, and at least one fan-out structure disposed on the second surface. Each scanning signal line extends along a first direction. Each group of shift register circuits includes a plurality of shift register circuits along a second direction. Each shift register circuit is coupled to a scanning signal line. The fan-out structure is coupled to the shift register circuits. At least one group of shift register circuits is disposed in a non-edge region of the display area. The shift register circuit disposed in the non-edge region is configured to transmit a scanning signal to the scanning signal line at both sides of the shift register circuit along the first direction.