Array Substrate Gate Line Connection via Multi-Layer Passivation
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Solution Overview
Problem
Conventional liquid crystal display (LCD) devices with liquid crystal capsules face challenges in achieving high resolution and improved aperture ratio and transmittance due to increased gaps between pixel regions, leading to reduced performance.
Innovation Solution
The implementation of an array substrate with gate lines connected using a different layer pattern, which reduces the gap between vertically adjacent pixel regions, enhances the aperture ratio, and improves transmittance by eliminating the need for additional gap margins between common and gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two gate lines are disposed between two vertically adjacent pixel regions, then the pixel regions are defined, but the gap between pixel regions increases and aperture ratio is reduced
Solution Approach 1:
The patent applies dimensionality change by moving the connection of gate lines from the planar dimension to the vertical dimension through multiple layers. Gate lines are connected via different layers (first connecting pattern on second passivation layer, second connecting pattern on third passivation layer) to reduce the gap between vertically adjacent pixel regions while maintaining proper definition of pixel regions.
2Manufacturing precision
If additional gap margins are added between common and gate lines, then manufacturing precision is improved, but the gap between pixel regions increases and resolution is reduced
Solution Approach 1:
The patent uses multi-layer connection patterns to resolve the conflict between gap margins and resolution. By connecting gate lines through different layers (second passivation layer, third passivation layer) rather than requiring larger planar gaps, the design maintains manufacturing precision while minimizing the impact on pixel region size and resolution.
3Ease of manufacture
If gate lines are connected using the same layer pattern, then manufacturing is simplified, but signal delay occurs and performance is reduced
Solution Approach 1:
The patent transitions from single-layer to multi-layer gate line connections. The first connecting pattern is formed on the second passivation layer and the second connecting pattern is formed on the third passivation layer, creating a three-dimensional connection structure that reduces signal delay while maintaining manufacturing feasibility through sequential layer formation.
Solution Approach 2:
The gate line connection is segmented into multiple discrete connection patterns across different layers. The first connecting pattern and second connecting pattern are separately formed on different passivation layers, allowing optimized signal paths and reducing overall signal delay while keeping each individual connection pattern manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a higher resolution display with improved aperture ratio and transmittance by minimizing the gap between pixel regions and preventing signal delay, thereby enhancing the overall performance of the LCD device.
Implementation Method 1
The LCD device displays an image using an optical anisotropy and a polarization property of a liquid crystal molecule
Implementation Method 2
The LCD device displays an image using an optical anisotropy and a polarization property of a liquid crystal molecule
Implementation Method 3
The LCD device including a liquid crystal capsule displays a gray level by changing an effective refractive index anisotropy (or an average refractive index anisotropy) according to an electric field
Data Source
AI summary
An array substrate for a display device includes: a substrate having a plurality of pixel regions; a plurality of gate lines on the substrate, each of the plurality of gate lines including a plurality of gate patterns spaced apart from each other; a plurality of data lines crossing the plurality of gate lines to define the plurality of pixel regions; and a first connecting pattern connecting the plurality of gate patterns, the first connecting pattern having a different layer from the plurality of gate lines.