Array Substrate Gate Line Segmentation for LCD Yield
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Solution Overview
Problem
In large liquid crystal display panels, the long gate lines are susceptible to electrostatic breakdown due to charge accumulation during manufacturing, leading to low yield and potential short circuits, and the use of parallel jumpers reduces pixel density.
Innovation Solution
The array substrate design includes connection portions and jumper portions in different layers, with intersecting extension directions, connected via vias, and bridge electrodes to reduce charge accumulation and maintain high pixel density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If long gate lines are used in large liquid crystal display panels, then the display area is increased, but charge accumulation occurs leading to electrostatic breakdown and low yield
Solution Approach 1:
The gate line is divided into multiple connection portions separated by jumper portions, creating segments that reduce charge accumulation in each segment while maintaining the overall long gate line structure for large display area
Solution Approach 2:
The gate line structure transitions from a single-layer planar layout to a multi-layer three-dimensional structure with connection portions and jumper portions in different layers, reducing charge accumulation without compromising display area
2Reliability
If parallel jumpers are used to connect gate line segments, then charge accumulation is reduced, but pixel density decreases
Solution Approach 1:
Jumper portions are positioned in different layers than connection portions, utilizing the third dimension (vertical layering) to connect gate line segments without occupying horizontal space that would reduce pixel density
Solution Approach 2:
The gate line is segmented into connection portions and jumper portions in different layers, allowing charge reduction functionality without compromising pixel density in the display region
Data Source
AI summary
Provided is an array substrate, including a substrate, a plurality of gate lines, and a plurality of sub-pixels. The gate line includes a plurality of connection portions and a plurality of jumper portions, which are alternately arranged and disposed in different layers. The connection portion includes a connection line segment, a first adapter line segment, and a second adapter line segment. One end of the connection line segment is connected to the first adapter line segment, and the other end is connected to the second adapter line segment. One end of the jumper portion, between adjacent two connection portions, is connected to an end, going away from the connection line segment, of the first adapter line segment in one of the connection portions, and the other end is connected to an end, going away from the connection line segment, of the second adapter line segment in the other connection portion.